A CMOS 160 Mb/s phase modulation I/O interface circuit
暂无分享,去创建一个
This paper proposes an approach to data transfer that can potentially achieve high rates without requiring the ultra fast clocks of other approaches, or extra wide buses. The idea is to transfer multiple bits over each pin within each clock cycle using modulation techniques common in communication systems. Phase modulation is simple in implementation and demonstrates 160 Mb/s peak transfer rate per pin using a 20 MHz clock. This scheme may prove effective for chip-to-chip or system bus interface both on printed circuit boards (PCBs) and multi-chip modules (MCMs).<<ETX>>
[1] Randy H. Katz,et al. Design of PLL-based clock generation circuits , 1987 .
[2] Bruce A. Wooley,et al. A BiCMOS time interval digitizer for high-energy physics instrumentation , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[3] Mark Horowitz,et al. PLL design for a 500 MB/s interface , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.