Computer Science (Computer Engineering)

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[35]  He Liu,et al.  Click Trajectories: End-to-End Analysis of the Spam Value Chain , 2011, 2011 IEEE Symposium on Security and Privacy.

[36]  Stijn Eyerman,et al.  Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware , 2011, (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.

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[48]  Steven Swanson,et al.  Beyond the datasheet: Using test beds to probe non-volatile memories' dark secrets , 2010, 2010 IEEE Globecom Workshops.

[49]  Paul H. Siegel,et al.  Error characterization and coding schemes for flash memories , 2010, 2010 IEEE Globecom Workshops.

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[52]  Arun Jagatheesan,et al.  Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

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[58]  Jihong Kim,et al.  BlueSSD: An Open Platform for Cross-layer Experiments for NAND Flash-based SSDs , 2010 .

[59]  Karin Strauss,et al.  Use ECP, not ECC, for hard failures in resistive memories , 2010, ISCA.

[60]  David A. Wood,et al.  WiDGET: Wisconsin decoupled grid execution tiles , 2010, ISCA.

[61]  Moinuddin K. Qureshi,et al.  Morphable memory system: a robust architecture for exploiting multi-level phase change memories , 2010, ISCA.

[62]  Yuxiong He,et al.  The Cilkview scalability analyzer , 2010, SPAA '10.

[63]  Feng Zhao,et al.  Virtual machine power metering and provisioning , 2010, SoCC '10.

[64]  José Ignacio Hidalgo,et al.  Thermal-aware floorplanning exploration for 3D multi-core architectures , 2010, GLSVLSI '10.

[65]  David J. Lilja,et al.  High performance solid state storage under Linux , 2010, 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST).

[66]  Hairong Kuang,et al.  The Hadoop Distributed File System , 2010, 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST).

[67]  Fang Liu,et al.  Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[68]  Hsien-Hsin S. Lee,et al.  An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

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[91]  Robert S. Germain,et al.  Using the Active Storage Fabrics model to address petascale storage challenges , 2009, PDSW '09.

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[97]  Erik Elmroth,et al.  Accounting and Billing for Federated Cloud Infrastructures , 2009, 2009 Eighth International Conference on Grid and Cooperative Computing.

[98]  Eui-Young Chung,et al.  Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices , 2009, IEEE Transactions on Consumer Electronics.

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[100]  Peter A. Dinda,et al.  Investigating virtual passthrough I/O on commodity devices , 2009, OPSR.

[101]  Tajana Simunic,et al.  PDRAM: A hybrid PRAM and DRAM main memory system , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[102]  Ronald Morrison,et al.  Orthogonal Persistence Revisited , 2009, ICOODB.

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[104]  Ralph Wittig,et al.  Performance and power of cache-based reconfigurable computing , 2009, ISCA '09.

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[106]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

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[108]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[109]  Xiaodong Zhang,et al.  Understanding intrinsic characteristics and system implications of flash memory based solid state drives , 2009, SIGMETRICS '09.

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[112]  Yo-Hwan Koh,et al.  A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[113]  Hong Ding,et al.  A 113mm2 32Gb 3b/cell NAND flash memory , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[114]  Khanh Nguyen,et al.  A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[115]  Henri Casanova,et al.  Resource Allocation Using Virtual Clusters , 2009, 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid.

[116]  Sang-Won Lee,et al.  A survey of Flash Translation Layer , 2009, J. Syst. Archit..

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[118]  Dongkun Shin,et al.  KAST: K-associative sector translation for NAND flash memory in real-time systems , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[119]  John Sartori,et al.  Distributed peak power management for many-core architectures , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[120]  Anand Sivasubramaniam,et al.  Statistical profiling-based techniques for effective power provisioning in data centers , 2009, EuroSys '09.

[121]  Antony I. T. Rowstron,et al.  Migrating server storage to SSDs: analysis of tradeoffs , 2009, EuroSys '09.

[122]  He Peng,et al.  Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network , 2009, 2009 10th International Symposium on Quality Electronic Design.

[123]  Thomas F. Wenisch,et al.  PowerNap: eliminating server idle power , 2009, ASPLOS.

[124]  Olivier Temam,et al.  Reconciling specialization and flexibility through compound circuits , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[125]  Onur Mutlu,et al.  Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[126]  Scott A. Mahlke,et al.  Bridging the computation gap between programmable processors and hardwired accelerators , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[127]  Rajeev Balasubramonian,et al.  Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[128]  Hyokyung Bahn,et al.  P/PA-SPTF: Parallelism-aware request scheduling algorithms for MEMS-based storage devices , 2009, TOS.

[129]  Steven Swanson,et al.  Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications , 2009, ASPLOS.

[130]  Youngjae Kim,et al.  DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.

[131]  Kern Koh,et al.  Comparison of I/O scheduling algorithms for high parallelism MEMS-based storage devices , 2009, ICSE 2009.

[132]  Jeremy Sugerman,et al.  GPU virtualization on VMware's hosted I/O architecture , 2008, OPSR.

[133]  John D. Davis,et al.  FRP: A Nonvolatile Memory Research Platform Targeting NAND Flash , 2009 .

[134]  Jack J. Dongarra,et al.  Collecting Performance Data with PAPI-C , 2009, Parallel Tools Workshop.

[135]  Luiz André Barroso,et al.  The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines , 2009, The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines.

[136]  Derek McAuley,et al.  Standardized But Flexible I/O for Self-Virtualizing Devices , 2008, Workshop on I/O Virtualization.

[137]  Muli Ben-Yehuda,et al.  Scalable I/O - A Well-Architected Way to Do Scalable, Secure and Virtualized I/O , 2008, Workshop on I/O Virtualization.

[138]  Lidong Zhou,et al.  Transactional Flash , 2008, OSDI.

[139]  Woong Hwan Ryu,et al.  Multi-GHZ modeling and characterization of on-chip power delivery network , 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

[140]  Amin Ansari,et al.  The StageNet fabric for constructing resilient multicore systems , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[141]  Onur Mutlu,et al.  Prefetch-Aware DRAM Controllers , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[142]  Engin Ipek,et al.  Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

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[144]  Jie Chen,et al.  Analysis and approximation of optimal co-scheduling on Chip Multiprocessors , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[145]  Li Shang,et al.  Multi-Optimization power management for chip multiprocessors , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[146]  Zhao Zhang,et al.  Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

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[148]  Jun Yang,et al.  Thermal Management for 3D Processors via Task Scheduling , 2008, 2008 37th International Conference on Parallel Processing.

[149]  Onur Mutlu,et al.  Distributed order scheduling and its application to multi-core dram controllers , 2008, PODC '08.

[150]  Andrew D. Gordon,et al.  Refinement Types for Secure Implementations , 2008, 2008 21st IEEE Computer Security Foundations Symposium.

[151]  Rina Panigrahy,et al.  Design Tradeoffs for SSD Performance , 2008, USENIX ATC.

[152]  Jae-Myung Kim,et al.  A case for flash memory ssd in enterprise database applications , 2008, SIGMOD Conference.

[153]  Scott A. Mahlke,et al.  DVFS in loop accelerators using BLADES , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[154]  M. Breitwisch.  Phase Change Memory , 2008, 2008 International Interconnect Technology Conference.

[155]  Onur Mutlu,et al.  Self-Optimizing Memory Controllers: A Reinforcement Learning Approach , 2008, 2008 International Symposium on Computer Architecture.

[156]  Scott A. Mahlke,et al.  VEAL: Virtualized Execution Accelerator for Loops , 2008, 2008 International Symposium on Computer Architecture.

[157]  Trevor N. Mudge,et al.  Improving NAND Flash Based Disk Caches , 2008, 2008 International Symposium on Computer Architecture.

[158]  Onur Mutlu,et al.  Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems , 2008, 2008 International Symposium on Computer Architecture.

[159]  Stijn Eyerman,et al.  System-Level Performance Metrics for Multiprogram Workloads , 2008, IEEE Micro.

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[161]  V. Kamakoti,et al.  Automatic Constraint Based Test Generation for Behavioral HDL Models , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[162]  Yeong-Taek Lee,et al.  A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.

[163]  Yookun Cho,et al.  Secure deletion for NAND flash file system , 2008, SAC '08.

[164]  Li-Pin Chang,et al.  A self-balancing striping scheme for NAND-flash storage systems , 2008, SAC '08.

[165]  Kevin Skadron,et al.  Scalable parallel programming , 2008, 2008 IEEE Hot Chips 20 Symposium (HCS).

[166]  David M. Brooks,et al.  Efficiency trends and limits from comprehensive microarchitectural adaptivity , 2008, ASPLOS.

[167]  Vanish Talwar,et al.  No "power" struggles: coordinated multi-level power management for the data center , 2008, ASPLOS.

[168]  Hyojun Kim,et al.  BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage , 2008, FAST.

[169]  Vivek Sarkar,et al.  Type inference for locality analysis of distributed data structures , 2008, PPoPP.

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[171]  Y. Iwata,et al.  Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[172]  Yan Solihin,et al.  A Framework for Providing Quality of Service in Chip Multi-Processors , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[173]  S. Winkel.  Optimal versus Heuristic Global Code Scheduling , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[174]  Onur Mutlu,et al.  Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

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[176]  V. Sundaram,et al.  Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package , 2007, IEEE Transactions on Advanced Packaging.

[177]  Daniel A. Connors,et al.  DracoSTM: a practical C++ approach to software transactional memory , 2007, LCSD '07.

[178]  Karsten Schwan,et al.  VirtualPower: coordinated power management in virtualized enterprise systems , 2007, SOSP.

[179]  Heeseung Jo,et al.  A group-based wear-leveling algorithm for large-capacity flash memory storage systems , 2007, CASES '07.

[180]  Won-Taek Lim,et al.  Effective Management of DRAM Bandwidth in Multicore Processors , 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).

[181]  Francisco J. Cazorla,et al.  MLP-Aware Dynamic Cache Partitioning , 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).

[182]  S. Ikeda,et al.  2Mb SPRAM Design: Bi-Directional Current Write and Parallelizing-Direction Current Read Schemes Based on Spin-Transfer Torque Switching , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[183]  Francisco J. Cazorla,et al.  Online Prediction of Applications Cache Utility , 2007, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

[184]  Sang-Won Lee,et al.  A log buffer-based flash translation layer using fully-associative sector translation , 2007, TECS.

[185]  Karsten Schwan,et al.  High performance and scalable I/O virtualization via self-virtualized devices , 2007, HPDC '07.

[186]  Milind Girkar,et al.  EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system , 2007, PLDI '07.

[187]  Jangho Park,et al.  Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[188]  Yan Solihin,et al.  QoS policies and architecture for cache/memory in CMP platforms , 2007, SIGMETRICS '07.

[189]  Engin Ipek,et al.  Core fusion: accommodating software diversity in chip multiprocessors , 2007, ISCA '07.

[190]  James E. Smith,et al.  Virtual private caches , 2007, ISCA '07.

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