Post-silicon verification and debugging with control flow traces and patchable hardware

In this paper we show three methods for postsilicon verification and debugging with control-flow analysis. By concentrating on control flows of SoC behavior, abstracted analysis can be applied and much significantly long time spans can be examined. The first method introduces monitoring methods of communications or transactions among cores inside SoCs. From the monitoring results, control sequences on interactions of cores are automatically determined to be used for post-silicon analysis. The second method shows algorithms to determine orderings of communications inside NoC (Network-on-Chip) used in SoCs. These analysis give information on how messages are transferred onto NoC, which are to be used for post-silicon analysis. The third method introduces trace buffers to compactly save state transition sequences of FSMs in the control parts of cores inside SoCs. By recognizing abnormal transitions, which is basically control flow analysis, both logical and electrical errors can be efficiently detected during postsilicon debug.

[1]  Leslie Lamport,et al.  Time, clocks, and the ordering of events in a distributed system , 1978, CACM.

[2]  Klaus D. McDonald-Maier,et al.  Debug support for complex systems on-chip: a review , 2006 .

[3]  Nicola Nicolici,et al.  Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation , 2008, 2008 Design, Automation and Test in Europe.

[4]  Kees G. W. Goossens,et al.  Transaction-Based Communication-Centric Debug , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[5]  Masahiro Fujita,et al.  Global transaction ordering in Network-on-Chips for post-silicon validation , 2011, 2011 12th International Symposium on Quality Electronic Design.

[6]  Nur A. Touba,et al.  Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[7]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[8]  Kees G. W. Goossens,et al.  A high-level debug environment for communication-centric debug , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[9]  Masahiro Fujita,et al.  An energy-efficient patchable accelerator for post-silicon engineering changes , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[10]  Masahiro Fujita,et al.  Transaction-based debugging of system-on-chips with patterns , 2009, 2009 IEEE International Conference on Computer Design.