Post-silicon verification and debugging with control flow traces and patchable hardware
暂无分享,去创建一个
[1] Leslie Lamport,et al. Time, clocks, and the ordering of events in a distributed system , 1978, CACM.
[2] Klaus D. McDonald-Maier,et al. Debug support for complex systems on-chip: a review , 2006 .
[3] Nicola Nicolici,et al. Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation , 2008, 2008 Design, Automation and Test in Europe.
[4] Kees G. W. Goossens,et al. Transaction-Based Communication-Centric Debug , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[5] Masahiro Fujita,et al. Global transaction ordering in Network-on-Chips for post-silicon validation , 2011, 2011 12th International Symposium on Quality Electronic Design.
[6] Nur A. Touba,et al. Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture , 2008, 26th IEEE VLSI Test Symposium (vts 2008).
[7] Daniel D. Gajski,et al. High ― Level Synthesis: Introduction to Chip and System Design , 1992 .
[8] Kees G. W. Goossens,et al. A high-level debug environment for communication-centric debug , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[9] Masahiro Fujita,et al. An energy-efficient patchable accelerator for post-silicon engineering changes , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[10] Masahiro Fujita,et al. Transaction-based debugging of system-on-chips with patterns , 2009, 2009 IEEE International Conference on Computer Design.