A 1.9GHz image-reject front-end with automatic tuning in a 0.15/spl mu/m CMOS technology

A 1.9GHz front-end consists of an LNA, an image-reject notch filter with automatic frequency and Q tuning circuits, and a down-conversion mixer. Implemented in a 0.15/spl mu/m CMOS process, the 0.45mm/sup 2/ front-end achieves 5.4dB noise figure, -12dBm IIP3 and consumes 19mW from 1.5V supply.

[1]  M. A. Copeland,et al.  A 1.9-GHz silicon receiver with monolithic image filtering , 1998 .

[2]  Yannis Tsividis,et al.  Integrated continuous-time filter design , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[3]  H.R. Rategh,et al.  A 5-GHz CMOS wireless LAN receiver front end , 2000, IEEE Journal of Solid-State Circuits.

[4]  M. D. McDonald A 2.5 GHz BiCMOS image-reject front-end , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Yannis Tsividis,et al.  Integrated continuous-time filter design - an overview , 1994, IEEE J. Solid State Circuits.

[6]  Sorin P. Voinigescu,et al.  5 GHz SiGe HBT monolithic radio transceiver with tunable filtering , 1999, 1999 IEEE Radio Frequency Integrated Circuits Symposium (Cat No.99CH37001).