Address equation multiplexing for real-time signal processing applications

This paper describes several sharing techniques, tuned to hardware address generation for large memories in real-time signal processing systems. These strategies are oriented to minimize the area overhead introduced by the use of application-specific address generation units. The objective is to explore at the system level, when the signal processing application is being defined, the trade-offs involved in alternative algorithmic specifications. This will allow one to arrive faster at area efficient specifications as input for the actual address hardware generation stage. The principles are demonstrated on a realistic test-vehicle for which very promising results have been achieved.

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