论文信息 - Timing Optimization for Virtual FPGA Configurations - 字舞流文

Timing Optimization for Virtual FPGA Configurations

Marco Platzner | Tobias Wiersema | Linus Witschen | Arne Bockhorn | Masood Raeisi Nafchi

[1] Marco Platzner,et al. An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip , 2016, Comput. Electr. Eng..

[2] Dominique Lavenier,et al. Placing, Routing, and Editing Virtual FPGAs , 2001, FPL.

[3] Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach , 2017, ARC.