New fast and area-efficient pipeline 3-D DCT architectures

Abstract The efficient implementation of 3-D transforms is a challenging task due to the computation complexity, memory and area requirements of such transforms. One important 3-D transform is the 3-D Discrete Cosine Transform (3-D DCT) used in many image and video processing systems. In this paper, two new pipeline architectures for the 3-D DCT computation using the 3-D DCT Vector-Radix algorithm (3-D DCT VR) are presented. These architectures are scalable and parameterisable with regards to different wordlengths and pipelining levels. Their arithmetic component requirements are reduced to the order of O ( log 2 ⁡ N ) in contrast with O ( N ) for 3-D DCT architectures in the literature, while at the same time they can keep similar or better area-time complexity.

[1]  Magdy A. Bayoumi,et al.  NEDA: a low-power high-performance DCT architecture , 2006, IEEE Transactions on Signal Processing.

[2]  Didier J. Le Gall,et al.  The MPEG video compression standard , 1991, Compcon.

[3]  Zhao Yan,et al.  Device-saving pipeline architectures of multi-dimensional DCT similar butterfly algorithm , 2016, 2016 International Conference on Integrated Circuits and Microsystems (ICICM).

[4]  Sergio Saponara Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec , 2010, Journal of Real-Time Image Processing.

[5]  Arjuna Madanayake,et al.  Algebraic integer based 8×8 2-D DCT architecture for digital video processing , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[6]  Mohammed Ghanbari,et al.  The accuracy of PSNR in predicting video quality for different video scenes and frame rates , 2012, Telecommun. Syst..

[7]  Swapna Banerjee,et al.  An Efficient Architecture for 3-D Discrete Wavelet Transform , 2010, IEEE Transactions on Circuits and Systems for Video Technology.

[8]  B. Zamanlooy,et al.  Design and implementation of a 118 MHz 2D DCT processor , 2008, 2008 IEEE International Symposium on Industrial Electronics.

[9]  Donald A. Adjeroh,et al.  Fast Three-Dimensional Discrete Cosine Transform , 2008, SIAM J. Sci. Comput..

[10]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1992 .

[11]  Sergio Saponara,et al.  Radar Sensor Signal Acquisition and Multidimensional FFT Processing for Surveillance Applications in Transport Systems , 2017, IEEE Transactions on Instrumentation and Measurement.

[12]  Basant K. Mohanty,et al.  Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT , 2011, IEEE Transactions on Signal Processing.

[13]  Toshiaki Miyazaki,et al.  3D-DCT Processor and Its FPGA Implementation , 2011, IEICE Trans. Inf. Syst..

[14]  Mohammed Ghanbari,et al.  Spatio-temporal scalability-based motion-compensated 3-D subband/DCT video coding , 2006, IEEE Transactions on Circuits and Systems for Video Technology.

[15]  Keshab K. Parhi,et al.  Parallel pipelined FFT architectures with reduced number of delays , 2012, GLSVLSI '12.

[16]  Zhongfeng Wang,et al.  An improved scaled DCT architecture , 2009, IEEE Transactions on Consumer Electronics.

[17]  Chunyan Wang,et al.  Recursive algorithm, architectures and FPGA implementation of the two-dimensional discrete cosine transform , 2008 .

[18]  Said Boussakta,et al.  Fast algorithm for the 3-D DCT-II , 2004, IEEE Transactions on Signal Processing.

[19]  Basant K. Mohanty,et al.  Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames , 2011, IEEE Transactions on Signal Processing.

[20]  S. C. Chan,et al.  Direct methods for computing discrete sinusoidal transforms , 1990 .

[21]  Weiping Li,et al.  Overview of fine granularity scalability in MPEG-4 video standard , 2001, IEEE Trans. Circuits Syst. Video Technol..

[22]  Jaakko Astola,et al.  Discrete cosine and sine transforms - regular algorithms and pipeline architectures , 2006, Signal Process..

[23]  L. Fanucci,et al.  Low-power VLSI architectures for 3D discrete cosine transform (DCT) , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[24]  Jiun-In Guo,et al.  A generalized architecture for the one-dimensional discrete cosine and sine transforms , 2001, IEEE Trans. Circuits Syst. Video Technol..

[25]  Amar Aggoun,et al.  Two-dimensional DCT/IDCT architecture , 2003 .

[26]  A. E. Salama,et al.  Implementation of 3D-DCT based video encoder/decoder system , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[27]  Amar Aggoun,et al.  A parallel 3D DCT architecture for the compression of integral 3D images , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[28]  Wen-Hsing Hsu,et al.  A Video Watermarking Technique Based on Pseudo-3-D DCT and Quantization Index Modulation , 2010, IEEE Transactions on Information Forensics and Security.

[29]  Gustavo de Veciana,et al.  An information fidelity criterion for image quality assessment using natural scene statistics , 2005, IEEE Transactions on Image Processing.

[30]  N. Chabini,et al.  Low power and fast DCT architecture using multiplier-less method , 2011, 2011 Faible Tension Faible Consommation (FTFC).

[31]  Sergio Saponara,et al.  Design of compact and low-power X-band Radar for mobility surveillance applications , 2016, Comput. Electr. Eng..

[32]  Said Boussakta,et al.  Pipeline Architectures for Radix-2 New Mersenne Number Transform , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  Donald A. Adjeroh,et al.  Balanced Multiple Description Coding for 3D DCT Video , 2011, IEEE Transactions on Broadcasting.

[34]  Saad Mohammed Saleh Al-Azawi,et al.  Efficient architectures for multidimensional discrete transforms in image and video processing applications , 2013 .

[35]  Zhao Yan,et al.  Three dimensional DCT similar butterfly algorithm and its pipeline architectures , 2016, 2016 IEEE Information Technology, Networking, Electronic and Automation Control Conference.

[36]  Saad Al-Azawi Low-Power, Low-Area Multi-level 2-D Discrete Wavelet Transform Architecture , 2018, Circuits Syst. Signal Process..

[37]  Hanzi Wang,et al.  Incremental Learning of 3D-DCT Compact Representations for Robust Visual Tracking , 2012, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[38]  A. Madisetti,et al.  DCT/IDCT processor design for HDTV applications , 1995, Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics.

[39]  Thomas Sri Widodo,et al.  FPGA implementation of pipelined 2D-DCT and quantization architecture for JPEG image compression , 2010, 2010 International Symposium on Information Technology.

[40]  Said Boussakta,et al.  Algorithms and pipeline architectures for 2-D FFT and FFT-like transforms , 2010, Digit. Signal Process..

[41]  Jiun-In Guo,et al.  Efficient parallel adder based design for one-dimensional discrete cosine transform , 2000 .

[42]  Tsin-Yuan Chang,et al.  A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[43]  Roger Woods,et al.  Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality , 2011, IET Comput. Digit. Tech..

[44]  Keshab K. Parhi,et al.  Pipelined Parallel FFT Architectures via Folding Transformation , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[45]  Razali Jidin,et al.  Low complexity multidimensional CDF 5/3 DWT architecture , 2014, 2014 9th International Symposium on Communication Systems, Networks & Digital Sign (CSNDSP).

[46]  Said Boussakta,et al.  Fast algorithm for the 3D DCT , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[47]  Li Niu,et al.  Implementation of 2-D DCT based on FPGA , 2010, International Conference on Image Processing and Pattern Recognition in Industrial Engineering.

[48]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[49]  Amar Aggoun,et al.  A 3D DCT architecture for compression of integral 3D images , 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

[50]  Ayman Alfalou,et al.  A low-power, high-speed DCT architecture for image compression: Principle and implementation , 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

[51]  Alex Yakovlev,et al.  High precision and low power DCT architectures for image compression applications , 2012 .