Interlock avoidance in transparent and dynamic parallel program instrumentation using logical clocks

A fundamental problem with run-time monitoring of parallel programs is the intrusion introduced by instrumenting the original program. In order to minimize the amount of intrusion in monitoring parallel programs, the logical clock approach (LCA) was proposed. It uses logical clocks to time and control the ordering of communication events during monitoring, and to reflect the real execution behavior when running without monitoring. However, the main problem with LCA is that in the case of non-deterministic communication and when several processes wait on each other's logical clock to advance, an interlock situation may occur, where none of the processes can continue to execute. This paper presents a strategy to avoid the interlock situations, based on the concept of ready condition. How the logical clocks are updated and communications are controlled in order to maintain the ordering of events, using a relaxed communication model, will be described. Compared with the original LCA, the new interlock avoidance approach is simpler and introduces less overhead. In addition, the modified logical clock mechanisms introduced in this paper are more general and applicable to a wider range of parallel computing systems.