On-site programmable gate array wire laying channel verification method and system thereof

A field programmable gate array (FPGA) wiring channel authentication method and a system relate integrated circuit technology. The method comprises steps below: 1) Predefining wiring channel testing vector for software, viz. an ideal result mapping table; 2) The software automatically creates configuration films one by one, transmits the configuration file to a hardware user FPGA for configuration, closes excessive wiring channel of the user FPGA, only conserves wiring channels to be tested, imposes a wiring channel testing channel to the hardware user FPGA according to a simulating vector, viz. the ideal result mapping table, conducts authentication and returns authentication results to the software; 3) The software analyzes comparison results and creates a testing report. The present invention avoids obtaining correct results while a plurality of errors are overlapped due to mutual impact, improves authentication speed and greatly increase testing efficiency.