Performance Analysis of Dynamic Reconfigurable Queues for High Speed Routers

New generation routers and switches have large amount of ports with each link operates at multiple Gbps. The equipped buffers for queues are usually huge for each router and switch. How to improve the buffer efficiency and minimize the required buffer size are great concerns for the design and implementation of packet switches. In this paper, we propose a dynamic reconfigurable buffer sharing scheme for an ideal non-blocking output queued packet switch based on SRAM-DRAM architecture. The SRAMs serve as interfaces between central memory and input/output links and will provide higher operation speed. The large main storage will be in DRAM. Using the scheme we proposed, buffer space to each port can be allocated dynamically according to their traffic load and queue status at runtime

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