Effect of scaling on noise in Circular Gate TFET and its application as a digital inverter

This paper reports the analysis of noise in Circular Gate TFET in presence of interface traps (Gaussian) when the device is subjected to scaling of gate-drain underlap length and body thickness, and change in gate work function and gate dielectric constant. TCAD simulations show that generation-recombination noise is dominant at low frequencies whereas diffusion noise is dominant at high frequencies. Flicker noise is found to be significant at low and medium frequencies. In order to comment on its reliability, the device is used in a Complementary TFET digital inverter circuit, and the transient characteristics are analyzed in presence of traps. The device exhibits excellent output at the inverter in absence of traps and in presence of low trap density, whereas voltage undershoot is observed when trap density is increased. SS degrades in presence of traps for various gate-drain underlap lengths in CG-TFET.On reducing body thickness, until it affects surface BTBT, Sid is not affected much.A lower źm or higher eox lowers the VGS at which the peak in Sid is observed.Dominance of noise at various frequencies- G-R: low; flicker: mid; diffusion: high.Higher traps cause higher undershoot % and fall time delay in CG-TFET inverter.