G-MPSoC: Generic Massively Parallel Architecture on FPGA

Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms (filtering, correlation, etc.) and their numerous parameters. Having a flexible and pro-grammable system that adapts to changing and various characteristics of these applications reduces the design cost. In this context, we propose in this paper Generic Massively Parallel architecture (G-MPSoC). G-MPSoC is a System-on-Chip based on a grid of clusters of Hardware and Software Computation Elements with different size, performance, and complexity. It is composed of parametric IP-reused modules: processor, controller, accelerator, memory, interconnection network, etc. to build different architecture configurations. The generic structure of G-MPSoC facilitates its adaptation to the intensive signal processing applications requirements. This paper presents G-MPSoC architecture and details its different components. The FPGA-based implementation and the experimental results validate the architectural model choice and show the effectiveness of this design.

[1]  Seth Hall,et al.  GPU-based Image Analysis on Mobile Devices , 2011, ArXiv.

[2]  Luca Benini,et al.  He-P2012: Architectural heterogeneity exploration on a scalable many-core platform , 2014, 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors.

[3]  Wayne Luk,et al.  A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation , 2009, FPGA '09.

[4]  Mouna Baklouti,et al.  Méthode de conception rapide d'architecture massivement parallèle sur puce : de la modélisation à l'expérimentation sur FPGA. (A rapid design method of a massively parallel System on Chip: from modeling to FPGA implementation) , 2010 .

[5]  Mohamed Abid,et al.  Broadcast with mask on a massively parallel processing on a chip , 2012, 2012 International Conference on High Performance Computing & Simulation (HPCS).

[6]  Piotr Dudek,et al.  An event-driven massively parallel fine-grained processor array , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[7]  Luca Benini,et al.  GPU Acceleration for Simulating Massively Parallel Many-Core Platforms , 2015, IEEE Transactions on Parallel and Distributed Systems.

[8]  Richard E. Haskell,et al.  A VHDL--Forth Core for FPGAs , 2004, Microprocess. Microsystems.

[9]  Steven L. Scott,et al.  Synchronization and communication in the T3E multiprocessor , 1996, ASPLOS VII.

[10]  Frank Hannig,et al.  Invasive Tightly-Coupled Processor Arrays , 2014, ACM Trans. Embed. Comput. Syst..

[11]  Mohamed Abid,et al.  Master-Slave Control Structure for Massively Parallel System on Chip , 2013, 2013 Euromicro Conference on Digital System Design.

[12]  W. Daniel Hillis,et al.  The Network Architecture of the Connection Machine CM-5 , 1996, J. Parallel Distributed Comput..

[13]  Luca Benini,et al.  He-P2012: Architectural heterogeneity exploration on a scalable many-core platform , 2014, ASAP.

[14]  John R. Nickolls,et al.  The design of the MasPar MP-1: a cost effective massively parallel computer , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.

[15]  Johan Andersson,et al.  A reconfigurable SIMD architecture on-chip , 2006 .

[16]  Kui Dai,et al.  Parallel Algorithms for FIR Computation Mapped to ESCA Architecture , 2010, 2010 WASE International Conference on Information Engineering.

[17]  Woon-Seng Gan,et al.  Digital Signal Processors: Architectures, Implementations, and Applications , 2004 .

[18]  Luca Benini,et al.  Platform 2012, a many-core computing accelerator for embedded SoCs: Performance evaluation of visual analytics applications , 2012, DAC Design Automation Conference 2012.