Circuit and method for clock signal generation

Circuit for generating an internal clock of a semiconductor device, with - a delay chain (100) having a plurality of delay units (178-189) which are made of RC delay elements or path gate elements constructed (178-189), for generating multiphase clocks from an input clock (CLK), - a selection decoder (200) for outputting a selection code value depending on selection data, which are supplied as binary code data from the outside, - a multiplexer (300) for selectively dispensing one of the plurality, supplied from the delay chain measures, depending on the selection code value, for which it performs the same a shared multiplexing with the selection code value in two stages by means of high-order bits and low order bits, and - a pulse regenerator (400) in the form of a short pulse type generator to restore a waveform of the output from the multiplexer clock.