Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing

Despite enabling significant performance improvements, reconfigurable computing systems have not gained widespread acceptance: most reconfigurable computing paradigms lack (1) a unified and transparent programming model, and (2) a standard interface for integration of hardware accelerators. Ideally, programmers should code algorithms and designers should write hardware accelerators independently of any detail of the underlying platform. We argue that achieving portability and uniform programming with only limited loss of performance is one of the main issues that hinder the widespread acceptance of reconfigurable computing. To make reconfigurable computing globally more attractive, we suggest a transparent, portable, and hardware agnostic programming paradigm. For achieving software code and hardware design portability, platform-specific tasks are delegated to a system-level virtualisation layer that supports a chosen programming model-much in the same way platform details are hidden from users in general-purpose computers. Although an additional abstraction inherently brings overheads, we show that the involvement of the virtualisation layer exposes potential optimisations that compensate the overheads and bring additional speedups. As a case-study, we present a real design and implementation of a number of building blocks of such system and discuss the challenges involved in materialising the others.

[1]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[2]  Giovanni De Micheli,et al.  Synthesis of hardware models in C with pointers and complex data structures , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[3]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[4]  André DeHon,et al.  The Density Advantage of Configurable Computing , 2000, Computer.

[5]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Donald E. Knuth,et al.  The Art of Computer Programming, Volume I: Fundamental Algorithms, 2nd Edition , 1997 .

[7]  Douglas J. Joseph,et al.  Prefetching Using Markov Predictors , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[8]  Paolo Ienne,et al.  Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors , 2004, FPL.

[9]  Giovanni De Micheli,et al.  Readings in hardware / software co-design , 2001 .

[10]  Marco Platzner,et al.  Object-oriented domain specific compilers for programming FPGAs , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Andreas Moshovos,et al.  Dependence based prefetching for linked data structures , 1998, ASPLOS VIII.

[12]  Michael Winston Dales,et al.  Managing a reconfigurable processor in a general purpose workstation environment , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[13]  Paolo Ienne,et al.  Virtual memory window for a portable reconfigurable cryptography coprocessor , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[14]  Anoop Gupta,et al.  Parallel computer architecture - a hardware / software approach , 1998 .

[15]  Erik R. Altman,et al.  LaTTe: a Java VM just-in-time compiler with fast and efficient register allocation , 1999, 1999 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00425).

[16]  Paolo Ienne,et al.  Virtual memory window for application-specific reconfigurable coprocessors , 2004, Proceedings. 41st Design Automation Conference, 2004..

[17]  Marco Platzner,et al.  Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations , 2003, Engineering of Reconfigurable Systems and Algorithms.