SEMICONDUCTOR INTEGRATED CIRCUITS: A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious free dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3.1 × 2.1 mm2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.

[1]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[2]  J. Bjornsen,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[3]  Jieh-Tsorng Wu,et al.  A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration , 2007, IEEE J. Solid State Circuits.

[4]  Lei Xie,et al.  A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications , 2008, IEEE Journal of Solid-State Circuits.

[5]  P.J. Hurst,et al.  A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration , 2004, IEEE Journal of Solid-State Circuits.

[6]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[7]  J. Kornblum,et al.  A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.

[8]  K. Bacrania,et al.  A 14-b linear capacitor self-trimming pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.

[9]  A.A. Abidi,et al.  A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR , 2000, IEEE Journal of Solid-State Circuits.

[10]  Shen-Iuan Liu,et al.  A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC , 2004 .

[11]  Bjørnar Hernes,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS , 2005 .

[12]  K. Bacrania,et al.  A 14 b 20 MSample/s CMOS pipelined ADC , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[13]  P.R. Gray,et al.  A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR , 2004, IEEE Journal of Solid-State Circuits.

[14]  F. Kuttner,et al.  A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13/spl mu/m CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[15]  Bang-Sup Song,et al.  A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching , 2007, IEEE Journal of Solid-State Circuits.

[16]  Seung-Hoon Lee,et al.  A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors , 2006, IEEE Custom Integrated Circuits Conference 2006.