Generalised approach to automatic custom layout of analogue ICs

An automatic custom analogue IC layout methodology is presented which employs primitive cell recognition, critical net analysis, and self-constructive floorplanning and routing techniques. Based on this methodology, a general-purpose analogue circuit module layout generator, SLAM, has been developed. Given the schematic netlist of an arbitrary analogue MOS circuit module, SLAM can quickly generate a high-quality custom layout to some desired aspect ratio. With a simple extension of the hierarchy, this method can also handle more complex analogue subsystems. Special layout constraints are automatically analysed for each analogue circuit and properly incorporated into the layout generation on each level of the circuit hierarchy to achieve both high performance and overall area efficiency. Experimental results on common analogue VLSI building blocks such as operational amplifier, comparator and neural circuit modules are presented.

[1]  Mohammed Ismail,et al.  Analog VLSI Implementation of Neural Systems , 2011, The Kluwer International Series in Engineering and Computer Science.

[2]  Bing J. Sheu,et al.  A compact and general-purpose neural chip with electrically programmable synapses , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[3]  Rob A. Rutenbar,et al.  Automatic layout of custom analog cells in ANAGRAM , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[4]  Bing J. Sheu,et al.  Knowledge-based analog circuit synthesis with flexible architecture , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[5]  J.E. Schroeder,et al.  Analog CMOS Building Blocks for Custom and Semicustom Applications , 1984, IEEE Journal of Solid-State Circuits.

[6]  Larry J. Stockmeyer,et al.  Optimal Orientations of Cells in Slicing Floorplan Designs , 1984, Inf. Control..

[7]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[8]  Walter S. Scott,et al.  Magic: A VLSI Layout System , 1984, 21st Design Automation Conference Proceedings.

[9]  C. Tomovich,et al.  MOSIS - A gateway to silicon , 1988, IEEE Circuits and Devices Magazine.

[10]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.