TIMBER: Time borrowing and error relaying for online timing error resilience

Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Two sequential circuit elements—TIMBER flip-flop and TIMBER latch—that implement error masking based on time-borrowing are described. Both circuit elements are validated using corner-case circuit simulations, and the overhead and trade-offs of TIMBER-based error masking are evaluated on an industrial processor.

[1]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[2]  Hiroaki Suzuki,et al.  Phase-adjustable Error Detection Flip-Flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[3]  Keith A. Bowman,et al.  Circuit techniques for dynamic variation tolerance , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[4]  Cecilia Metra,et al.  Sensing circuit for on-line detection of delay faults , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Alice Wang,et al.  Adaptive Techniques for Dynamic Processor Optimization , 2008 .

[6]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[7]  David Blaauw,et al.  Timing yield enhancement through soft edge flip-flop based design , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[8]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[9]  Kartik Mohanram,et al.  Masking timing errors on speed-paths in logic circuits , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[10]  Edward J. McCluskey,et al.  On-line delay testing of digital circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[11]  Gu-Yeon Wei,et al.  Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency , 2009, IEEE Micro.

[12]  Toshinori Sato,et al.  A Simple Flip-Flop Circuit for Typical-Case Designs for DFM , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[13]  Massoud Pedram,et al.  A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[14]  Sotirios Matakias,et al.  A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[15]  Josep Torrellas,et al.  ReCycle:: pipeline adaptation to tolerate process variation , 2007, ISCA '07.

[16]  K.A. Bowman,et al.  Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[17]  Dimitris Gizopoulos,et al.  Concurrent Delay Testing in Totally Self-Checking Systems , 1998, J. Electron. Test..

[18]  Shuichi Sakai,et al.  Delay-Compensation Flip-Flop with In-situ Error Monitoring for Low-Power and Timing-Error-Tolerant Circuit Design , 2008 .

[19]  Cecilia Metra,et al.  On-line detection of logic errors due to crosstalk, delay, and transient faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[20]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..