论文信息 - Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

We report a two-dimensional (2D) pixel block scanning architecture for image segmentation by segment growing. This architecture can optimize processing speed, power consumption, and circuit area by modifying size and shape of the pixel block. Real-time processing can be maintained by using additional the two important techniques of (i) boundary-scan of the grown segment only, (ii) continued block-internal segment growing. We analyze and optimize the size and shape trade-offs for the pixel block, and evaluate the proposed architecture by an FPGA. Altogether, the investigated architecture concepts reduce the area-time product by 52.3 % in comparison to a previously reported one-dimensional (1D) scanning architecture.

[1] Hans Jürgen Mattausch,et al. Object tracking in video pictures based on image segmentation and pattern matching , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[2] Hans Jürgen Mattausch,et al. Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation , 2004, IEICE Trans. Inf. Syst..

[3] Tsuyoshi Koyama,et al. Theoretical analysis of available range in alignment procedure for linear surgical tools using projection of intersecting two laser planes and accuracy validation (Medical Imaging) , 2004 .

[4] Masahiko Yoshimoto,et al. VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation , 2006, IEICE Trans. Electron..

[5] Liang-Gee Chen,et al. Efficient moving object segmentation algorithm using background registration technique , 2002, IEEE Trans. Circuits Syst. Video Technol..