Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems

An intrinsic notion of quality floors present in typical digital signal processing circuits can be used to strategically accept some runtime errors in exchange for a reduction in energy consumption. Conventional very large scale integration design strategies do not exploit this degree of error tolerance and aim to guarantee timing correctness, thereby sacrificing energy efficiency. In this paper, we propose techniques for timing error acceptance to improve the quality-energy tradeoff in image and video processing systems under scaled $V_{DD}$. The basic philosophy is to prevent signal quality from severe degradation, on average, by using data statistics. The introduced innovations include techniques for carefully controlling possible errors and exploiting the specifics of error patterns for low-cost postprocessing to minimize quality degradation. We demonstrate the effectiveness of the proposed techniques on a 2-D inverse discrete cosine transform (IDCT) and a 2-D DCT design. The designs were synthesized using a 45-nm standard cell library, with energy and delay evaluated using NanoSim and VCS. Experiments show that direct applications of controlled error-acceptance techniques allow up to 59% and 71% energy savings by permitting fewer than 1-dB peak signal-to-noise ratio (PSNR) decrease for the 2-D IDCT and DCT designs, respectively. The resulting PSNR remains above 30dB, which is a commonly accepted value for lossy image and video compression. Achieving such energy savings by direct $V_{DD}$ scaling without the proposed transformations results in a 12-dB PSNR loss. The area overhead for the needed control logic is about 4.8% of the original design. To further minimize quality degradation caused by accepted errors in the IDCT, we introduce postfiltering on the output image. The significant improvement of the perceived image quality allows further voltage scaling leading to overall energy savings of 70% for the 2-D IDCT, while costing an additional 1.1% in area.

[1]  Izzat Darwazeh,et al.  Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Gian Carlo Cardarilli,et al.  Imprecise arithmetic for low power image processing , 2012, 2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR).

[3]  Anantha Chandrakasan,et al.  Approximate Signal Processing , 1997, J. VLSI Signal Process..

[4]  Naresh R. Shanbhag,et al.  Low-power filtering via adaptive error-cancellation , 2003, IEEE Trans. Signal Process..

[5]  R. K. Richards,et al.  Arithmetic operations in digital computers , 2013 .

[6]  A. Chandrakasan,et al.  A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization , 1999, IEEE Journal of Solid-State Circuits.

[7]  A. P. Chandrakasan,et al.  Energy efficient filtering using adaptive precision and variable voltage , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[8]  Masahiko Yoshimoto,et al.  A 100-MHz 2-D discrete cosine transform core processor , 1992 .

[9]  Yiannis Andreopoulos,et al.  Software Designs of Image Processing Tasks With Incremental Refinement of Computation , 2010, IEEE Transactions on Image Processing.

[10]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[11]  Kaushik Roy,et al.  System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning , 2009, 2009 IEEE Workshop on Signal Processing Systems.

[12]  Yang Liu,et al.  Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Kaushik Roy,et al.  Process Variation Tolerant Low Power DCT Architecture , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[14]  D. Donoho,et al.  Does median filtering truly preserve edges better than linear filtering , 2006, math/0612422.

[15]  Yang Liu,et al.  On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[16]  Anantha P. Chandrakasan,et al.  Low-power digital filtering using approximate processing , 1996 .

[17]  Ku He,et al.  Controlled timing-error acceptance for low energy IDCT design , 2011, 2011 Design, Automation & Test in Europe.

[18]  Eero P. Simoncelli,et al.  Image quality assessment: from error visibility to structural similarity , 2004, IEEE Transactions on Image Processing.

[19]  Naresh R. Shanbhag,et al.  Soft digital signal processing , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Kaushik Roy,et al.  Low power reconfigurable DCT design based on sharing multiplication , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[21]  Kaushik Roy,et al.  CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Joseph W. Goodman,et al.  A mathematical analysis of the DCT coefficient distributions for images , 2000, IEEE Trans. Image Process..

[23]  Ahmed M. Eltawil,et al.  Low-Power Multimedia System Design by Aggressive Voltage Scaling , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Keith R. Dimond,et al.  A hardware FPGA implementation of a 2D median filter using a novel rank adjustment technique , 1999 .