Efficient data management on 3D stacked memory for big data applications

Big data processing has been an increasingly important field which has attracted a lot of attention from academia and industry. However, it worsens the memory wall problem for processor design, which means a large performance gap between processor computation and memory access. The 3D stacked memory structure has been put forward as a promising method to relieve this problem. As non-volatile memory(NVM) become available and common nowadays, they can be fused into the 3D memory structure to provide a fast and large memory. DRAM + NVM have been designed as a novel, faster and larger memory structure. Flash is the maturest NVM material currently so that flash takes the role of NVM in our experiment. However, as DRAM has totally different characteristics from Flash, such combined structure shows bad support for big data applications. Thus, efficient data manage strategies are greatly needed. We implemented two data manage strategies(granularity strategy (GS) and Read/Write partition strategy (RWPS)) to improve performance. Our experiment results are very positive. When using 64 channels, GS can improve performance by 11.3%, and the RWPS can improve performance by 20.4%. Combined the two strategies together, the performance can be increased by 26.1%. In addition, for RWPS, it can obviously increase the write performance by 29.8% because of its novel design.

[1]  Yiran Chen,et al.  Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[2]  Harish Patil,et al.  Pin: building customized program analysis tools with dynamic instrumentation , 2005, PLDI '05.

[3]  Jianhua Li,et al.  ExLRU: A unified write buffer cache management for flash memory , 2011, 2011 Proceedings of the Ninth ACM International Conference on Embedded Software (EMSOFT).

[4]  Stefan K. Lai,et al.  Flash memories: Successes and challenges , 2008, IBM J. Res. Dev..

[5]  Jaeha Kim,et al.  Memory-centric system interconnect design with Hybrid Memory Cubes , 2013, Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques.

[6]  Krishna M. Kavi,et al.  New Memory Organizations for 3D DRAM and PCMs , 2012, ARCS.

[7]  Nisha Talagala,et al.  HEC: improving endurance of high performance flash-based cache devices , 2013, SYSTOR '13.

[8]  Gang Lu,et al.  CloudRank-D: benchmarking and ranking cloud computing systems for data processing applications , 2012, Frontiers of Computer Science.

[9]  Steven Swanson,et al.  Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications , 2009, ASPLOS.

[10]  J. Thomas Pawlowski,et al.  Hybrid memory cube (HMC) , 2011, 2011 IEEE Hot Chips 23 Symposium (HCS).

[11]  Krishna M. Kavi,et al.  3D DRAM and PCMs in Processor Memory Hierarchy , 2014, ARCS.

[12]  Bruce Jacob,et al.  DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.

[13]  Feifei Li,et al.  NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads , 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[14]  Michael M. Swift,et al.  FlashTier: a lightweight, consistent and durable storage cache , 2012, EuroSys '12.

[15]  Youngjae Kim,et al.  FlashSim: A Simulator for NAND Flash-Based Solid-State Drives , 2009, 2009 First International Conference on Advances in System Simulation.