论文信息 - A 102-dB spurious-free DR /spl Sigma//spl Delta/ ADC using a dynamic dither scheme

A 102-dB spurious-free DR /spl Sigma//spl Delta/ ADC using a dynamic dither scheme

A sigma-delta analog-to-digital converter (ADC) using dynamic dither to achieve a tone-free dynamic range of 102 dB in an audio bandwidth is presented. The design was implemented using a third-order 2:1 cascade architecture with an oversampling ratio of 128. The ADC modulator consumes 22 mW from a 3.0 V power supply, and was fabricated in 0.6-/spl mu/m CMOS (analog portion) and 0.3-/spl mu/m CMOS (digital portion) using multichip-module technology.

G. J. Gomez

[1] Steven Robert Norsworthy. Dynamic Dithering of Delta-Sigma Modulators , 1995 .

[2] David Arthur Rich,et al. Idle Channel Tones and Dithering in Delta-Sigma Modulators , 1993 .

[3] Bruce A. Wooley,et al. A low-power, area-efficient digital filter for decimation and interpolation , 1994, IEEE J. Solid State Circuits.

[4] G. Temes. Delta-sigma data converters , 1994 .

[5] R. Schreier,et al. Delta-sigma data converters : theory, design, and simulation , 1997 .

[6] Bruce A. Wooley,et al. A third-order sigma-delta modulator with extended dynamic range , 1994 .