On the bit synchronization in digital communication systems using partial response signalling

An analysis of the symbol synchronization problem in digital communication systems using partial response signalling is presented. A series of approximations of the maximum-likelihood function, leading to the discrete symbol timing loop realizations are presented and discussed. Numerical analysis of the phase error discriminator characteristic for different configurations of the symbol synchronizer suggests the utilization of the signal limiting (sgn x-function) in these circuits. This is a way to eliminate the severe impact of the asymmetry of the signal trajectories on the system performance. A comprehensive analysis of a discrete realization of the symbol synchronizer is also presented.<<ETX>>