A general semiconductor press modeling framework

A general semiconductor process modeling framework is presented. The framework encompasses, first, a methodology for the description of any manufacturing process using state and state transformation information and, second, a conceptual process model that distinguishes between and defines terms for the state information and state transformations involved in integrated circuit fabrication. This modeling methodology and conceptual semiconductor process model aid in the understanding of fabrication processes, provide a formalism for the description of processes, help to guide the development of process flow languages and representations, and support a number of process-related activities, including process design and process control. >

[1]  J.D. Shott,et al.  The future of automation for high-volume Wafer fabrication and ASIC manufacturing , 1986, Proceedings of the IEEE.

[2]  J. M. Tenenbaum,et al.  A framework for knowledge-based computer-integrated manufacturing , 1989 .

[3]  Robert W. Dutton,et al.  A manufacturing-oriented environment for synthesis of fabrication processes , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  A. S. Grove,et al.  General Relationship for the Thermal Oxidation of Silicon , 1965 .

[5]  Ruey-Shan Guo,et al.  Process control system for VLSI fabrication , 1991 .

[6]  Michael L. Heytens,et al.  The intertool profile interchange format: an object-oriented approach [semiconductor technology CAD/CAM] , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  C.-Y. Fu,et al.  Smart integrated circuit processing , 1989 .

[8]  Duane S. Boning,et al.  Integrating semiconductor process design and manufacture using a unified process flow representation , 1990, [1990] Proceedings. Rensselaer's Second International Conference on Computer Integrated Manufacturing.

[9]  A. Neureuther,et al.  A general simulator for VLSI lithography and etching processes: Part I—Application to projection lithography , 1979, IEEE Transactions on Electron Devices.

[10]  Duane S. Boning,et al.  CAFE-the MIT computer aided fabrication environment , 1990 .

[11]  Robert W. Dutton,et al.  Verification of analytic point defect models using SUPREM-IV [dopant diffusion] , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  R.W. Dutton,et al.  VLSI Process modeling—SUPREM III , 1983, IEEE Transactions on Electron Devices.

[13]  Chiakang Sung,et al.  A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etching , 1980, IEEE Transactions on Electron Devices.