Performance Enhancement of Pipeline ADCs

..................................................................................................................iii ACKNOWLEDGMENTS.......................................................................................v DEDICATION.................................................................................................vi LIST OF TABLES.............................................................................................x LIST OF FIGURES............................................................................................xi CHAPTER

[1]  Dongtian Lu High speed CMOS ADC for UWB receiver , 2007 .

[2]  L. Singer,et al.  A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[3]  Yawei Guo,et al.  A 1.8-V 22-mW 10-bit 30-MS/s Subsampling , 2006 .

[4]  Dong Wang,et al.  Background interstage gain calibration technique for pipelined ADCs , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Degang Chen,et al.  Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Kari Halonen,et al.  1-V 9-bit pipelined switched-opamp ADC , 2001 .

[7]  M. Timko,et al.  A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[8]  G. Promitzer 12 bit low power fully differential switched capacitor non-calibrating successive approximation ADC with 1MS/s , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[9]  David G. Nairn A 10-bit, 3V, 100M§/s Pipelined ADC , 2000 .

[10]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[11]  Bang-Sup Song,et al.  A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering , 2008, IEEE Journal of Solid-State Circuits.

[12]  Y. Chiu High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS , 2004 .

[13]  M.R. Ahmad,et al.  Design of Single-Stage Folded-Cascode Gain Boost Amplifier for 100mW 10-bit 50MS/s Pipelined Analog-to-Digital Converter , 2006, 2006 IEEE International Conference on Semiconductor Electronics.

[14]  Hae-Seung Lee A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC , 1994 .

[15]  Shuo Yang,et al.  Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs , 2010, Microelectron. J..

[16]  S. Hamami,et al.  CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC , 2007 .

[17]  Zhu Zhangming,et al.  SHA-less architecture with enhanced accuracy for pipelined ADC , 2012 .

[18]  李平,et al.  A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR , 2012 .

[19]  Ian Galton,et al.  Digital Background Correction of Harmonic Distortion in Pipelined ADCs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Peter Händel,et al.  Dynamic characterization of analog-digital-converters , 2007 .

[21]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[22]  Bahar Jalali Farahani,et al.  Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCs , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[23]  Solomon Max Fast accurate and complete ADC testing , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[24]  Kari Halonen,et al.  A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[25]  Stephen H. Lewis,et al.  Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications , 1992 .

[26]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[27]  Ian Galton,et al.  Gain error correction technique for pipelined analogue-to-digital converters , 2000 .

[28]  K. Cheng,et al.  A BIST scheme for on-chip ADC and DAC testing , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[29]  Mrinal Das,et al.  Improved design criteria of gain-boosted CMOS OTA with high speed optimizations , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[30]  A.P. Chandrakasan,et al.  A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs , 2006, IEEE Journal of Solid-State Circuits.

[31]  Jonathan Yu,et al.  Charge Injection and Clock Feedthrough , 2010 .

[32]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[33]  Ting Li,et al.  A Digital Calibration Algorithm with Variable-Amplitude Dithering for Domain-Extended Pipeline ADCs , 2014 .

[34]  J. Kornblum,et al.  A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.

[35]  S.P. Voinigescu,et al.  A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees , 2009, IEEE Journal of Solid-State Circuits.

[36]  Yu Lin Yield and performance enhancement of analog and mixed signal circuits , 2006 .

[37]  Un-Ku Moon,et al.  Digital Calibration Techniques for Pipelined ADC ’ s , 1997 .

[38]  Luca Konig,et al.  Design With Operational Amplifiers And Analog Integrated Circuits , 2016 .

[39]  I. Mehr,et al.  A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 1999, IEEE Journal of Solid-State Circuits.

[40]  Robert W. Brodersen,et al.  Background ADC calibration in digital domain , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[41]  Gin-Kou Ma,et al.  SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration , 2011, IEEE Journal of Solid-State Circuits.