论文信息 - Reconfigurable address generators for stream-based computation implemented on FPGAs

Reconfigurable address generators for stream-based computation implemented on FPGAs

This paper describes the design and implementation of an address generator for stream-based computation. The unit can generate addresses by a 1, 2 or 3-dimensional mapping from a linear data string in memory. A processing unit will get the required data in a continuous stream without empty time slots, even when switching between addressing algorithms. Each algorithm is specified by a set of parameters loaded into FIFOs in background. The unit is specified by VHDL, simulated, synthesized and implemented on an FPGA of type Xilinx Virtex-II Pro. A speed of 144 MHz is obtained for generating 36 bit addresses. Ideas for expanding the flexibility of the unit are discussed.

Oddvar Søråsen | Kjetil E. Vistnes

[1] Reiner W. Hartenstein,et al. NOVEL SEQUENCER HARDWARE FOR HIGH-SPEED SIGNAL PROCESSING , 1998 .

[2] Liang-Gee Chen,et al. Reconfigurable discrete wavelet transform architecture for advanced multimedia systems , 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

[3] John Wawrzynek,et al. Stream Computations Organized for Reconfigurable Execution (SCORE) , 2000, FPL.

[4] Reiner W. Hartenstein,et al. An Embedded Accelerator for Real World Computing , 1997 .

[5] Seth Copen Goldstein,et al. PipeRench: a co/processor for streaming multimedia acceleration , 1999, ISCA.

[6] Jim Tørresen,et al. High Performance Computing by Context Switching Reconfigurable Logic , 2002, ESM.

[7] V. Michael Bove,et al. Stream-Based Computing and Future Television , 1995 .

[8] John Wawrzynek,et al. Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial , 2000 .