Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

Abstract The effect of scaling on electrostatic discharge (ESD) robustness in 1.2 to 0.25 μm channel length CMOS technologies is explored for ESD protection circuits and MOSFET structures. Results show that ESD robustness decreases as ESD structures are scaled to smaller dimensions in future technologies. Technology benchmarking, using a standardized ESD design, for evaluating ESD robustness is discussed. The ESD sensitivity of ESD designs to geometrical and semiconductor process parameters are evaluated. An analytical development for electro-thermal failure is developed based on electro quasi-static and adiabatic assumptions. ESD scaling relationships are developed applying MOSFET constant electric field scaling theory. ESD robustness scales as 1/α 3 2 , where α is the scaling parameter. The scaling relationship derived from the analytical model is then compared to established power-to-failure ESD models. The impact of MOSFET scaling on the ESD robustness of MOSFET structures is then discussed. MOSFET scaling as a function of technology generation shows that snapback breakover and sustaining voltages are decreasing with each technology generation. Optimization, design constraints and technology tradeoffs in CMOS technology development are then shown using a design curve methodology.