High performance and low cost implementation of Fast Fourier Transform algorithm based on Hardware Software co-design

The paper presents a high performance implementation of Fast Fourier Transform (FFT) algorithm using the notion of Hardware Software Partitioning. The co-design methodology was used to achieve higher system performance and design flexibility. The algorithm was originally implemented on a microcontroller (Atmegal6) but suffered from high execution delay. A low cost reconfigurable device like Spartan-3E Field Programmable Gate Array (FPGA) was then used to overcome this shortcoming, but the algorithm failed to be implemented on it, due to limited number of configurable logic blocks available within the capacity of the FPGA. Finally, a novel architecture has been realized based on hardware software partition with respect to implementation on microcontroller and FPGA together, such that the two devices communicate with each other, run synergistically and ensure optimality in power, delay and area. Also, a comparative study of the power dissipation, execution delay, area of implementing FFT on the different architectures: first, completely sequential (software), second, completely parallel, i.e. hardware (using FPGA) and third based on Hardware Software Co-design is performed. The power consumption of the co-design has been found to be 0.072W at a supply voltage 3.3V.

[1]  A. O. Fernandes,et al.  Hardware-software codesign of embedded systems , 1998, Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216).

[2]  Juan A. Michell,et al.  FPGA realization of a split radix FFT processor , 2007, SPIE Microtechnologies.

[3]  D. Cohen.  Simplified control of FFT hardware , 1976 .

[4]  Steven G. Johnson,et al.  A Modified Split-Radix FFT With Fewer Arithmetic Operations , 2007, IEEE Transactions on Signal Processing.

[5]  Theerayod Wiangtong,et al.  Multitasking in hardware-software codesign for reconfigurable computer , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[6]  T. Bially,et al.  Parallelism in fast Fourier transform hardware , 1973 .

[7]  Hossam Fahmy,et al.  Optimized hardware implementation of FFT processor , 2009, 2009 4th International Design and Test Workshop (IDT).

[8]  Viktor Öwall,et al.  Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  M. Puschel,et al.  FFT Program Generation for Shared Memory: SMP and Multicore , 2006, ACM/IEEE SC 2006 Conference (SC'06).

[10]  Muniandi Kannan,et al.  Hardware implementation low power high speed FFT core , 2009, Int. Arab J. Inf. Technol..

[11]  Paul Ehrlich,et al.  Energy-aware software development for embedded systems in HW/SW co-design , 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[12]  Rajesh Gupta,et al.  Hardware/software co-design , 1996, Proc. IEEE.

[13]  Edward A. Lee,et al.  A hardware-software codesign methodology for DSP applications , 1993, IEEE Design & Test of Computers.

[14]  Jubee Tada,et al.  Complex Multiplier Suited for FPGA Structure , 2008 .

[15]  C. Loan.  Computational Frameworks for the Fast Fourier Transform , 1992 .

[16]  Rajesh Gupta,et al.  Hardware Software Co-Design of Embedded Systems , 1996, VLSI Design.

[17]  J. Tukey,et al.  An algorithm for the machine calculation of complex Fourier series , 1965 .

[18]  Steven G. Johnson,et al.  The Design and Implementation of FFTW3 , 2005, Proceedings of the IEEE.