Defect level evaluation in an IC design environment

The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to nonequiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models. It is shown that DL depends on the critical areas associated with undetected faults, and their correspondent defect densities. Simulation results are presented, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality. Moreover, results show that the efficiency of a given set of test patterns strongly depends on the physical design and defect statistics.

[1]  Francesco Corsi,et al.  Inductive fault analysis revisited , 1991 .

[2]  Francesco Corsi,et al.  Defect level as a function of fault coverage and yield , 1993, Proceedings ETC 93 Third European Test Conference.

[3]  D. M. H. Walker,et al.  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Charles F. Hawkins,et al.  CMOS IC fault models, physical defect coverage, and I/sub DDQ/ testing , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[5]  Marcel Jacomet,et al.  Fantestic: towards a powerful fault analysis and test pattern generator for integrated circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[6]  Robert C. Aitken,et al.  THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%? , 1991, 1991, Proceedings. International Test Conference.

[7]  Francesco Corsi,et al.  Critical areas for finite length conductors , 1992 .

[8]  João Paulo Teixeira,et al.  Physical design of testable CMOS digital integrated circuits , 1991 .

[9]  João Paulo Teixeira,et al.  Physical DFT for High Coverage of Realistic Faults , 1992, Proceedings International Test Conference 1992.

[10]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[11]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[12]  Prathima Agrawal,et al.  Fault coverage requirement in production testing of LSI circuits , 1982 .

[13]  J. P. Teixeira,et al.  Defect level estimation for digital ICs , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[14]  F. Joel Ferguson.  Physical design for testability for bridges in CMOS circuits , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[15]  Wojciech Maly,et al.  Physically realistic fault models for analog CMOS neural networks , 1991 .

[16]  J. Pineda de Gyvez,et al.  Systematic Extraction of Critical Areas From IC Layouts , 1990 .

[17]  João Paulo Teixeira,et al.  On the design of a highly testable cell library , 1992, Microprocess. Microprogramming.

[18]  João Paulo Teixeira,et al.  A methodology for testability enhancement at layout level , 1991, J. Electron. Test..

[19]  Feller William,et al.  An Introduction To Probability Theory And Its Applications , 1950 .

[20]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.

[21]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[22]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[23]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[24]  João Paulo Teixeira,et al.  IC DEFECTS-BASED TESTABILITY ANALYSIS , 1991, 1991, Proceedings. International Test Conference.

[25]  F. Joel Ferguson,et al.  Carafe: an inductive fault analysis tool for CMOS VLSI circuits , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[26]  G. Spiegel.  Fault probabilities in routing channels of VLSI standard cell designs , 1994, Proceedings of IEEE VLSI Test Symposium.