SVM 기반 실시간 사물 인식을 위한 고성능 벡터 내적 연산 회로 설계

This paper describes the architecture and design of high-performance vector inner product computation circuit for real-time object recognition based on SVM. SVM algorithm was proposed by Vladimir Vapnik and AT&T Bell Laboratory teams and has higher detection rate than any other algorithms in object recognition. However, it is quite complex and requires huge amount of computational efforts. Consequently, it is important to implement an object recognition circuit to achieve real-time processing capability. The proposed vector inner product computation circuit makes it possible to recognize objects in real time based on SVM. The pipeline architecture with 6 stages is adopted to increase the operating speed. We described the proposed circuit using Verilog HDL and synthesized the gate-level circuit using TSMC 180nm standard cell library and fabricated MPW chip for verification. A real-time object recognition circuit based on SVM can be implemented by using the proposed vector inner product computation circuit.