Loop-based leakage control for branch predictors

Leakage energy consumption is becoming an important design consideration with the scaling of technology. Besides caches, branch predictors are among the largest on-chip array structures and consume non-trivial leakage energy. This paper proposes two loop-based strategies to reduce the branch predictor leakage without impacting prediction accuracy, which is crucial for achieving high performance. The loop-based approaches exploit the fact that loops usually only contain a small number of instructions and hence fewer branch instructions. Consequently, all the non-active entries of branch predictors can be placed into the low leakage mode during the loop execution for leakage energy savings. Compilers can annotate this information and pass it to the processor for reducing leakage at runtime. Compared to the recently-proposed decay-based approach, our experimental results show that the loop-based approach can extract 16.2% more branch predictor idleness on average, leading to more leakage energy savings without impacting the branch prediction accuracy and performance.