CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells

A novel technique, <italic>CLIP</italic>, is presented for the automatic generation of optimal layouts of <italic>CMOS</italic> cells in the two-dimensional (2D) style. <italic>CLIP</italic> is based on integer-linear programming (<italic>ILP</italic>) and solves both the width and height minimization problems for 2D cells. Width minimization is formulated in a precise form that combines all factors influencing the 2D cell width—transistor placement, diffusion sharing, and vertical interrow connections—in a common problem space; this space is then searched in a systematic manner by the branch-and-bound algorithms used by <italic>ILP</italic> solvers. For height minimization, cell height is modeled accurately in terms of the horizontal wire routing density, and a minimum-height layout is found from among all layouts of minimum width. For exact width minimization alone, <italic>CLIP</italic>'s run times are in seconds for large circuits with 30 or more transistors. For both height and width optimization, <italic>CLIP</italic> is practical for circuits with up to 20 transistors. To extend <italic>CLIP</italic> to larger circuits, hierarchical methods are necessary. Since <italic>CLIP</italic> is optimum under the modeling assumptions, its layouts are significantly better than those generated by other, heuristic, layout tools.