Adaptive explicitly parallel instruction computing

Current processors are programmed through a fixed interface called the Instruction Set Architecture (ISA). Consequently, a compiler targeting such a processor is forced to choose instructions from the provided instruction set. Often this instruction set is not a suitable match for the computational requirements of the application program. With in this context, we ask ourselves the following questions. (1) Can application performance be improved if the compiler had the freedom to wick the instruction set on a per application basis? (2) Can we build cost-effective processors that provide the ability to efficiently emulate compiler determined instruction sets and yet are not application specific? (3) Given that the desired processor capabilities are feasible, can the compiler determine an optimal set of instructions for a given application and generate code that can effectively exploit the processor capabilities? In this thesis, we provide sufficient evidence to answer these questions in the affirmative. Through a combination of architectural innovations and novel compilation techniques, this dissertation demonstrates that it is possible to attain significant improvement in performance, on general purpose and multimedia applications over comparable fixed ISA processors. First half of this dissertation describes this novel class of architectures, focusing on a specific subclass called Adaptive Explicitly Parallel Instruction Computing (ASPIC) architectures whose definition represents a collection of ideas intended to enable efficient reconfiguration of processor data paths. While ASPIC processor reconfiguration is affected by the executing program at runtime, the decisions of when and how to reconfigure are determined by the compiler and embedded in the application's executable. In the second half, a compilation framework targeting ASPIC processors is proposed. Several key compilation problems that need to be addressed in order to target ASPIC processors such as partitioning, instruction synthesis, configuration selection, resource allocation and scheduling are defined and efficient techniques for solving them are proposed. Finally, we describe the design of a simulation and performance monitoring framework for ASPIC architectures. How such architectures can be used to improve application performance is demonstrated using a set of programs from the SPEC and MediaBench benchmarks. Experimental results indicate the significant role architectural features of ASPIC processors play in masking the overheads of micro-architectural reconfiguration.

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