Static Power Reduction Techniques for Asynchronous Circuits

Power gating techniques are effective in mitigatingleakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two representative techniques, Cut-Off and Zig-Zag Cut-Off [1], and find that they offer an average of 80% and 20% in power savings, respectively, for asynchronous circuit families. We also present a new zero-delay (ZDRTO) wakeup technique for power gated asynchronous pipelines, which leverages the robustness of asynchronous circuits to delays and supply voltage variations.Our ZDRTO technique offers a tradeoff between wakeup timeand static power reduction, making it suitable for power gating pipelines with low-duty cycle, bursty usage patterns.

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