Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability

IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard's TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chip's scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard's basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features.

[1]  Dilip K. Bhavsar,et al.  Testability access of the high speed test features in the Alpha 21264 microprocessor , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[2]  J. Nadir,et al.  Computer aided design and built in self test on the i486 CPU , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[3]  Lee Whetsel A Proposed Method of Accessing 1149.1 in a Backplane Environment , 1992, Proceedings International Test Conference 1992.

[4]  Don Douglas Josephson,et al.  Test features of the HP PA7100LC processor , 1993, Proceedings of IEEE International Test Conference - (ITC).

[5]  Rajiv Patel,et al.  Testability Features of the SuperSPARCtm , 1993 .

[6]  Rajiv Patel,et al.  Testability features of the SuperSPARC microprocessor , 1993, Proceedings of IEEE International Test Conference - (ITC).

[7]  T.H. Lee,et al.  A 600 MHz superscalar RISC microprocessor with out-of-order execution , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[8]  Dilip K. Bhavsar An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes , 1991, 1991, Proceedings. International Test Conference.