The SoC (System-on-Chip) design for the WSN (Wireless Sensor Networks) nodes is the most significant technology of modern WSN design. There are a large amount of nodes in a WSN system, the nodes are densely deployed either inside the environment or very close to it. Each node is equipped with a sensor, an ADC (Analog-to-Digital Converter), a MCU (Micro Controller Unit), a storage unit, a power management unit, and a RF (Radio-Frequency) transceiver, as shown in Fig. 1, so that it can sense, store, process, and communicate with other sensors using multi-hop packet transmissions. The basic specifications of WSN are reliability, accuracy, flexibility, expenses, the difficulty of development and power consumption. Because all the nodes are battery-powered, power consumption is the most important specification of WSN. The core part of a WSN node is the RF transceiver, which is used to realize the wireless communication among the nodes. For a common used commercial chip, the distribution of power consumption is shown in Fig. 2, where TX and RX represent the transmitting mode and receiving mode of the transceiver. We can see that the RF part consumes the most power. Besides, modern RF design is composed of so many subjects that it requires IC designers to have sufficient knowledge. As a result, the IC design of RF transceivers becomes the most challenging research topic in the WSN field. As the applications of WSN become more and more widespread, many companies have developed highly-integrated chips for RF transceivers. The main specifications of several commercial chips are shown in Table. 1. The common characters of these chips can be summarized into several aspects: 1)a low data rate, 2)low power consumption, 3)high sensitivity, 4)relatively low output power, and 5)a simple modulation scheme. There are several ways to achieve low power consumption in WSN: 1)reduce the radiated power by using ad-hoc networks and multi-hop communication, 2)optimize the trade-off between communication and local computing, 3)design more power-efficient RF transceivers, and 4)develop more energy-efficient protocols and routing algorithms. And the third one is what we will talk about in this chapter. 1
[1]
Jri Lee,et al.
A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly
,
2009,
IEEE Journal of Solid-State Circuits.
[2]
B. Zhang,et al.
A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS
,
2003,
IEEE J. Solid State Circuits.
[3]
Qizheng Gu,et al.
RF System Design of Transceivers for Wireless Communications
,
2005
.
[4]
R. Castello,et al.
A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner
,
2005,
IEEE Journal of Solid-State Circuits.
[5]
Sudipto Chakraborty,et al.
A 2mW CMOS MICS-band BFSK transceiver with reconfigurable antenna interface
,
2010,
2010 IEEE Radio Frequency Integrated Circuits Symposium.
[6]
Michael H. Perrott,et al.
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
,
1997,
IEEE J. Solid State Circuits.
[7]
M. Steyaert,et al.
An analog integrated polyphase filter for a high performance low-IF receiver
,
1995,
Digest of Technical Papers., Symposium on VLSI Circuits..
[8]
S. Gambini,et al.
A 52 $\mu$ W Wake-Up Receiver With $-$ 72 dBm Sensitivity Using an Uncertain-IF Architecture
,
2009,
IEEE Journal of Solid-State Circuits.
[9]
Huazhong Yang,et al.
A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler
,
2009
.