Multi-pads, single layer power net routing in VLSI circuits

An algorithm is presented for obtaining a planar routing of two power nets in building-block layout. In contrast to other works, more than one pad for each of the power nets is allowed. First, conditions are established to guarantee a planar routing. The algorithm consists of three parts, a top-down terminal clustering, a bottom-up topological path routing, and a wire-width calculation procedure. Because of the hierarchical nature of the algorithm, it is inherently fast.<<ETX>>