New Low-Power Architectures of Support Vector Machine Classifier for Speech Recognition System

This paper proposes two architectures for an Artificial Intelligence (AI) algorithm applied in hardware. We have a first asynchronous proposal, 10-stage pipeline architecture, and a second proposal, Globally Asynchronous Locally Synchronous (GALS) pipeline architecture, for Support Vector Machine (SVM) non-linear classifier prototyped in a Field Programmable Gate Array (FPGA) – INTEL-ALTERA device. The training dataset was generated from a Hybrid Training Algorithm implemented in Matlab Software. Such an algorithm is composed of the Particle Swarm Optimization (PSO) algorithm application, followed by the SVM Training. For the speech signal pre-processing part, techniques of Mel-frequency Cepstral Coefficients (MFCCs) extraction and Discrete Cosine Transform were used. The whole idea was to develop an Automatic Speech Recognition (ASR) System with minimum use of the area as possible, low power consumption, and minimum human intervention. The first and second proposals results were, respectively, 30.79mW and 36.28mW of power consumption, 4.6%, and 2.1% of used LUTs. In recognition success rate, both proposals achieved 99% accuracy.