Performance and Variations Induced by Single Interface Trap of Nanowire FETs at 7-nm Node

DC/AC performance and the variations due to single interface trap of the nanowire (NW) FETs were investigated in the 7-nm technology node using fully calibrated TCAD simulation. Shorter junction gradient and greater diameter reduced <italic>RC</italic> delay without short channel degradations. Spacer with smaller dielectric constants decreased parasitic and gate capacitances with a slight decrease of ON-state currents, thus minimizing <italic>RC</italic> delay. Interface traps for the variability analysis were <inline-formula> <tex-math notation="LaTeX">${P}_{b0}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">${P}_{b1}$ </tex-math></inline-formula>, and fixed oxide charges at the Si/SiO<sub>2</sub> interface. <inline-formula> <tex-math notation="LaTeX">${P}_{b0}$ </tex-math></inline-formula> negligibly affected dc variations but <inline-formula> <tex-math notation="LaTeX">${P}_{b1}$ </tex-math></inline-formula> at the drain underlap regions increased gate-induced drain leakage currents, which induced greater OFF-state current variations. Fixed oxide charges, especially at the middle of the channel regions, shifted drain currents toward left by bending the energy band downward locally near the single interface trap. To maximize the performance as well as to minimize the variations induced by the interface traps, careful surface treatment for the drain underlap regions and adaptation of vertical NW structure are needed while maintaining fine short channel characteristics.

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