New Single Edge Triggered Flip-Flop Design with Improved Power and Power Delay Product for Low Data Activity Applications

The paper proposed a new design for implementing a Single Edge Triggered Flip-Flop. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. In the proposed design the number of clocked transistors is reduced to decrease the power consumption and it also employs the conditional feedback to reduce the short-circuit currents. All simulations are performed on Tspice using BSIM models in 130 nm process node. As compared to the other state of the art single edge triggered flip-flop designs, the newly proposed design is the best energy efficient having the best PDP having an improvement of up to 55.74% and 61.82% in view of power consumption and PDP, respectively. The proposed flip-flop also has the second best area. The simulation results show that the proposed flip-flop is best suited for low power and high performance especially for low data activity applications.