Automatic test pattern generation for industrial circuits with restrictors

Abstract This paper extends state-of-the-art automatic test pattern generation (ATPG) systems by including constraints, called restrictors, on the allowable values of the bits of a test pattern. Such restrictors often occur in industrial circuits where certain combinations of bit positions of a test pattern have to take on a particular value (e.g. in the case of a reset line) or are prohibited from taking on a particular value (e.g. in order to prevent an illegal state to be entered) (F. Hapke and R. Reche, Amsal reference manual, Technical Report , Philips GmbH, Hamburg, 1989). This paper describes the types of restrictors, as encountered in industrial circuits; it shows the required modifications to ATPG algorithms for stuck-at faults in circuits; in order to cope with restrictors and, finally, the results of experiments determining the consequences for the ATPG time and fault coverage are given. The overall conclusions are: restrictors can easily be implemented in any ATPG system; the use of restrictors is essential in industrial circuits; the influence of restrictors on the ATPG time is small, while a new class of “redundant faults” is identified, belonging to that part of the circuit which cannot be tested due to the specified restrictors.