论文信息 - Jitter peaking investigation in charge pump based clock and data recovery circuits

Jitter peaking investigation in charge pump based clock and data recovery circuits

Jitter transfer function of a clock and data recovery circuit (CDR) must satisfy difficult specifications versus of loop bandwidth and jitter peaking. This paper describes the method of setting poles and zero in third order CDR circuit to keep jitter peaking below a certain value required by specific optical standards. The results are validated by MATLAB simulations for a 10 Gb I s clock and data recovery circuit with an approximately 1MHz bandwidth.

R.E. Atani | A. Abrishamifar | F. Samii

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