Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument Modules

An extremely dense high-speed serial interface validation tester is presented. By relying on parallelism and on efficient measurement techniques, the proposed tester significantly reduces the time to validate the key parameters for serdes interfaces such as the bit error rate, receiver sensitivity, receiver jitter tolerance, and transmit jitter generation. Key timing specifications include periodic jitter injection with less than 5 psec edge-placement resolution and jitter measurement with 160 fsec sampling delay resolution

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