Integrated low-ripple-voltage fast-response switched-capacitor power converter with interleaving regulation scheme

This paper presents a new integrated switched-capacitor (SC) power converter with an interleaving regulation scheme. By dividing the original power stage into sub-units and operating each sub-unit in an interleaving way, both output ripple voltage and load transient response are largely improved without compromising other design parameters. The closed-loop operation with interleaving analog PWM control enables the converter to be accurately regulated at any desired levels. The design was submitted for fabrication in 0.35 mum CMOS N-well process. The entire die area including pads and power transistors is 3.52 mm2 . HSPICE post-layout simulation shows that, with a power supply of 1.5 V and a load of 250 mA, the converter is regulated at 2.5 V with an output ripple of 7 mV and the maximum efficiency of 83.2%. The converter responds to an 85-mA load change within 3 mus with 22-mV voltage variation

[1]  J. F. Dickson,et al.  On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique , 1976 .

[2]  Angela Arapoyanni,et al.  A CMOS charge pump for low voltage operation , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[3]  Janusz A. Starzyk,et al.  A DC-DC charge pump design based on voltage doublers , 2001 .

[4]  David J. Perreault,et al.  Distributed interleaving of paralleled power converters , 1997 .