Zur Validierung der Spezifikationen von videobildverarbeitenden Komponenten unter realen Anwendungsbedingungen

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[1]  Manfred Glesner,et al.  Neurocomputers: an overview of neural networks in VLSI , 1994 .

[2]  P. K. Bondyopadhyay,et al.  Moore's law governs the silicon revolution , 1998, Proc. IEEE.

[3]  Torsten Lehmann,et al.  An analog CMOS chip set for neural networks with arbitrary topologies , 1993, IEEE Trans. Neural Networks.

[4]  Dan W. Patterson,et al.  Artificial Neural Networks: Theory and Applications , 1998 .

[5]  Guozhong An,et al.  The Effects of Adding Noise During Backpropagation Training on a Generalization Performance , 1996, Neural Computation.

[6]  Geoffrey E. Hinton,et al.  Learning internal representations by error propagation , 1986 .

[7]  Bing J. Sheu,et al.  Neural information processing and VLSI , 1995 .

[8]  John Wawrzynek,et al.  The design of a neuro-microprocessor , 1993, IEEE Trans. Neural Networks.

[9]  Franz J. Rammig Systematischer Entwurf digitaler Systeme , 1989 .

[10]  Christian Lehmann,et al.  A generic systolic array building block for neural networks with on-chip learning , 1993, IEEE Trans. Neural Networks.

[11]  James A. Anderson,et al.  Neurocomputing: Foundations of Research , 1988 .

[12]  C. S. George Lee,et al.  Neural fuzzy systems: a neuro-fuzzy synergism to intelligent systems , 1996 .

[13]  H. T. Kung Use of VLSI in algebraic computation: Some suggestions , 1981, SYMSAC '81.

[14]  Alexander Moopenn,et al.  Digital-Analog Hybrid Synapse Chips for Electronic Neural Networks , 1989, NIPS.

[15]  Yves Chauvin,et al.  Backpropagation: theory, architectures, and applications , 1995 .

[16]  Grant E. Hearn,et al.  A Modified Learning Algorithm for Backpropagation Network , 1993 .

[17]  Fukumi,et al.  A new back-propagation algorithm with coupled neuron , 1989 .

[18]  H. C. Zeidler,et al.  On-chip backpropagation training using parallel stochastic bit streams , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[19]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[20]  John Kim,et al.  Active drag reduction using neural networks , 1996, Proceedings of International Workshop on Neural Networks for Identification, Control, Robotics and Signal/Image Processing.

[21]  Charles M. Bachmann,et al.  Neural Networks and Their Applications , 1994 .

[22]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[23]  Bart Kosko,et al.  Neural networks and fuzzy systems: a dynamical systems approach to machine intelligence , 1991 .

[24]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[25]  John Gilmore,et al.  Cracking DES - secrets of encryption research, wiretap politics and chip design: how federal agencies subvert privacy , 1998 .

[26]  Arch C. Luther Principles of digital audio and video , 1997 .

[27]  Andreas G. Andreou,et al.  Current-mode subthreshold MOS circuits for analog VLSI neural systems , 1991, IEEE Trans. Neural Networks.

[28]  Mohammed Ismail,et al.  Analog VLSI Implementation of Neural Systems , 2011, The Kluwer International Series in Engineering and Computer Science.

[29]  Otto Limann Fernsehtechnik ohne Ballast : Einführung in die Schaltungstechnik der Fernsehempfänger , 1963 .

[30]  Alan F. Murray,et al.  Integrated pulse stream neural networks: results, issues, and pointers , 1992, IEEE Trans. Neural Networks.

[31]  Mona E. Zaghloul,et al.  VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells , 1992, IEEE Trans. Neural Networks.

[32]  P. Werbos,et al.  Beyond Regression : "New Tools for Prediction and Analysis in the Behavioral Sciences , 1974 .

[33]  Douglas J. Smith,et al.  HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog , 1998 .

[34]  Anton Gunzinger,et al.  Achieving supercomputer performane for neural net simulation with an array of digital signal processors , 1992, IEEE Micro.

[35]  Roland E. Best Phase-Locked Loops , 1984 .

[36]  Amos R. Omondi,et al.  Computer arithmetic systems - algorithms, architecture and implementation , 1994, Prentice Hall International series in computer science.

[37]  A. Rost,et al.  Grundlagen der elektronik , 1983 .

[38]  B. Widrow,et al.  The truck backer-upper: an example of self-learning in neural networks , 1989, International 1989 Joint Conference on Neural Networks.

[39]  Andreas Zell,et al.  Simulation neuronaler Netze , 1994 .

[40]  Thomas Kropf,et al.  Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.

[41]  Takeshi Sakata,et al.  A single 1.5-V digital chip for a 106 synapse neural network , 1993, IEEE Trans. Neural Networks.

[42]  Carsten Wolff Parallele Simulation großer pulscodierter neuronaler Netze , 2001 .

[43]  T. Watanabe,et al.  Neural network simulation on a massively parallel cellular array processor: AAP-2 , 1989, International 1989 Joint Conference on Neural Networks.

[44]  S. Tam,et al.  An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapses , 1990, International 1989 Joint Conference on Neural Networks.

[45]  Bernd Girod,et al.  Einführung in die Systemtheorie , 1997 .

[46]  Dean A. Pomerleau,et al.  Neural Network Perception for Mobile Robot Guidance , 1993 .

[47]  Yann LeCun,et al.  Une procedure d'apprentissage pour reseau a seuil asymmetrique (A learning scheme for asymmetric threshold networks) , 1985 .

[48]  Yasuji Sawada,et al.  Functional abilities of a stochastic logic neural network , 1992, IEEE Trans. Neural Networks.

[49]  Markus Höhfeld,et al.  Learning with limited numerical precision using the cascade-correlation algorithm , 1992, IEEE Trans. Neural Networks.

[50]  Jack L. Meador,et al.  Programmable impulse neural circuits , 1991, IEEE Trans. Neural Networks.

[51]  Alexander Singer Exploiting the Inherent Parallelism of Artificial Neural Networks to Achieve 1300 Million Interconnects per Second , 1990 .

[52]  W. Press,et al.  Numerical Recipes: The Art of Scientific Computing , 1987 .

[53]  Bart Kosko,et al.  Neural networks for signal processing , 1992 .

[54]  K.-D. Kammeyer,et al.  Digitale Signalverarbeitung - Filterung und Spektralanalyse , 1989 .

[55]  William H. Press,et al.  The Art of Scientific Computing Second Edition , 1998 .

[56]  Lloyd W. Massengill,et al.  An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control , 1992, IEEE Trans. Neural Networks.

[57]  P. Lafrance,et al.  Digital filters , 1974, Proceedings of the IEEE.

[58]  Stephen Wolfram,et al.  Das Mathematica Buch - die offizielle Dokumentation: Mathematica Version 3 (3. Aufl.) , 1997 .

[59]  K. Lagemann,et al.  NeNEB-an application adjustable single chip neural network processor for mobile real time image processing , 1996, Proceedings of International Workshop on Neural Networks for Identification, Control, Robotics and Signal/Image Processing.

[60]  Dean Pomerleau,et al.  ALVINN, an autonomous land vehicle in a neural network , 2015 .

[61]  T. Kohonen,et al.  New developments and applications of self-organizing maps , 1996, Proceedings of International Workshop on Neural Networks for Identification, Control, Robotics and Signal/Image Processing.

[62]  Hugh D. Luke Signalubertragung: Grundlagen Der Digitalen Und Analogen Nachrichtenubertragungssysteme , 1995 .

[63]  Peter B. Denyer,et al.  Silicon Compilation , 1986, ESSCIRC '86: Twelfth European Solid-State Circuits Conference.

[64]  P. J. Plauger The Standard C Library , 1991 .

[65]  I N Bronstein,et al.  Taschenbuch der Mathematik , 1966 .

[66]  Maurice Bellanger,et al.  Digital processing of signals , 1989 .

[67]  D A Durfee,et al.  Comparison of floating gate neural network memory cells in standard VLSI CMOS technology , 1992, IEEE Trans. Neural Networks.

[68]  Ehud D. Karnin,et al.  A simple procedure for pruning back-propagation trained neural networks , 1990, IEEE Trans. Neural Networks.

[69]  Edward A. Rietman,et al.  Back-propagation learning and nonidealities in analog neural network hardware , 1991, IEEE Trans. Neural Networks.

[70]  Yannis P. Tsividis,et al.  A Reconfigurable Analog VLSI Neural Network Chip , 1989, NIPS.

[71]  Geoffrey E. Hinton,et al.  Learning representations by back-propagating errors , 1986, Nature.

[72]  Gerd Kock,et al.  MiND: An Environment for the Development, Integration, and Acceleration of Connectionist Systems , 1997 .

[73]  Anders Krogh,et al.  Introduction to the theory of neural computation , 1994, The advanced book program.

[74]  Jayaram Bhasker,et al.  A VHDL Synthesis Primer , 1996 .

[75]  James L. McClelland,et al.  Parallel Distributed Processing: Explorations in the Microstructure of Cognition : Psychological and Biological Models , 1986 .

[76]  David Lawrence Johannsen Silicon compilation , 1989 .

[77]  W. Pitts,et al.  A Logical Calculus of the Ideas Immanent in Nervous Activity (1943) , 2021, Ideas That Created the Future.

[78]  S. Sahu,et al.  SPHINX: a high level synthesis system for DSP design , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[79]  Raúl Rojas,et al.  Theorie der neuronalen Netze , 1993 .

[80]  Janet Wiles,et al.  The N-2-N Encoder: A Matter of Representation , 1993 .

[81]  Neuro-ASIC for low cost supervision of water pollution , 1996, Proceedings of International Workshop on Neural Networks for Identification, Control, Robotics and Signal/Image Processing.

[82]  John J. Hopfield,et al.  Neural networks and physical systems with emergent collective computational abilities , 1999 .

[83]  B. A. Bowen,et al.  VLSI systems design for digital signal processing , 1982 .

[84]  Reinhard Männer,et al.  Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1 , 1993, Int. J. Neural Syst..

[85]  John J. Paulos,et al.  The Effects of Precision Constraints in a Backpropagation Learning Network , 1990, Neural Computation.

[86]  F. A. Seiler,et al.  Numerical Recipes in C: The Art of Scientific Computing , 1989 .

[87]  Jayaram Bhasker A Verilog HDL Primer , 1997 .

[88]  R. Rauscher,et al.  An A/D-chip for accurate power measurement , 1991, Euro ASIC '91.

[89]  Jerzy B. Lont Analog CMOS implementation of a multi-layer perceptron with nonlinear synapses , 1992, IEEE Trans. Neural Networks.

[90]  Pierre Bricaud,et al.  Reuse methodology manual for system-on-chip designs , 1998 .

[91]  L. Rabiner,et al.  FIR digital filter design techniques using weighted Chebyshev approximation , 1975, Proceedings of the IEEE.

[92]  Bernard Widrow,et al.  Adaptive switching circuits , 1988 .

[93]  Paul Molitor,et al.  Einführung in den VLSI-Entwurf , 1989, Leitfäden und Monographien der Informatik.

[94]  Pran Kurup,et al.  Logic Synthesis Using Synopsys , 1995 .

[95]  Norman Hendrich Mustererkennung mit neuronalen Assoziativspeichernetzen , 1996, DISKI.

[96]  Ronald C. Stogdill Dealing with Obsolete Parts , 1999, IEEE Des. Test Comput..

[97]  E. Fiesler,et al.  Hardware-friendly learning algorithms for neural networks: an overview , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[98]  David Pellerin,et al.  VHDL Made Easy , 1996 .

[99]  Klaas Hoen,et al.  20 Million Patterns Per Second VLSI Neural Network Pattern Classifier , 1993 .

[100]  L. Larsson An EPLD Based Transient Recorder for Simulation of Video Signal Processing Devices in an VHDL Environment Close to System Level Conditions , 1996, FPL.

[101]  John Lazzaro,et al.  Analog VLSI model of binaural hearing , 1991, IEEE Trans. Neural Networks.

[102]  James A. Anderson,et al.  A simple neural network generating an interactive memory , 1972 .

[103]  James L. McClelland,et al.  Parallel distributed processing: explorations in the microstructure of cognition, vol. 1: foundations , 1986 .

[104]  E. Capaldi,et al.  The organization of behavior. , 1992, Journal of applied behavior analysis.

[105]  Norman Hendrich A scalable architecture for binary couplings attractor neural networks , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[106]  Bernard Widrow,et al.  Sensitivity of feedforward neural networks to weight errors , 1990, IEEE Trans. Neural Networks.

[107]  William A. Fisher,et al.  A programmable analog neural network processor , 1991, IEEE Trans. Neural Networks.

[108]  Peter Marwedel,et al.  Synthese und Simulation von VLSI-Systemen - Algorithmen für den rechnerunterstützten Entwurf hochintegrierter Schaltungen , 1993, Hanser-Studien-Bücher.

[110]  Keith Jack,et al.  Video Demystified: A Handbook for the Digital Engineer , 1993 .

[111]  Stephen I. Gallant,et al.  Perceptron-based learning algorithms , 1990, IEEE Trans. Neural Networks.

[112]  L. Y. Pratt,et al.  Case studies in the use of a hyperplane animator for neural network research , 1994, Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94).

[113]  Alan F. Murray,et al.  Pulse-stream VLSI neural networks mixing analog and digital techniques , 1991, IEEE Trans. Neural Networks.

[114]  M. Costa,et al.  Applying Backpropagation through Time to a Real Inverted Pendulum Problem , 1997 .

[115]  Teuvo Kohonen,et al.  Correlation Matrix Memories , 1972, IEEE Transactions on Computers.

[116]  Corporate Intel Corp. 386 Sx Microprocessor Programmer's Reference Manual , 1990 .

[117]  J. Hopfield Neurons withgraded response havecollective computational properties likethoseoftwo-state neurons , 1984 .

[118]  J. Cloutier,et al.  Hardware implementation of the backpropagation without multiplication , 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.

[119]  Raúl Rojas,et al.  The fractal geometry of backpropagation , 1994, Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94).

[120]  F ROSENBLATT,et al.  The perceptron: a probabilistic model for information storage and organization in the brain. , 1958, Psychological review.

[121]  S. Esener,et al.  A scalable optoelectronic neural system using free-space optical interconnects , 1992, IEEE Trans. Neural Networks.

[122]  Herbert Reininger,et al.  Hybrid number representation for the FPGA-realization of a versatile neuro-processor , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

[123]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .