An efficient and compact row buffer architecture on FPGA for real-time neighbourhood image processing

This work presents a compact and efficient row buffer (RB) architecture on field-programmable gate array (FPGA). The design confines multiple RBs within the full capacity of Xilinx Block RAM (BRAM) in contrast to the conventional approach which partially utilizes a full BRAM per RB. The configuration of BRAM with different port aspect ratio and its data accessing via an efficient pattern generator circuitry allows the design to buffer pixelwise image data and retrieve multiple pixels per clock in a predefined pattern to achieve the functionality of multiple RBs. The design uses smallest BRAM18 primitive to be scaled in small steps for any larger kernel and image size for providing the best economical solution. The proposed architecture retains the bandwidth requirement to 1 pixel/clock at an ideal efficiency of 1 clock/pixel along with the saving of up to 87.5% BRAMs as compared to the conventional RBs and at the same time sustains high frame rates ($$1920\times 1080$$1920×1080 @ 217 fps) to support real-time image processing. Therefore, it is feasible to replace conventional high-cost RBs with our proposed RBs on latest FPGA devices especially for high performance yet area constraint neighbourhood image processing applications.