FPGA (field programmable gate array) processor and PID (proportion integration differentiation) membrane optimization neural network controller

The invention provides a FPGA (field programmable gate array) processor and a PID (proportion integration differentiation) membrane optimization neural network controller. The FPGA processor comprises a particle distribution unit, a particle update unit, an optimal particle obtaining unit, a logic judgment unit. The particle distribution unit is used for distributing alternative solutions of equivalent particles to multiple layers of basic membrane. Each layer of basic membrane includes at least one particle. The particle update unit is used for calculating fitness value of the particles, updating inertia weight of each layer of basic membrane, and updating speed value and location value of each particle according to the fitness value and the inertia weight. The optimal particle obtaining unit is used for obtaining the optimal particle according to the fitness value, the speed value and the location value of each particle. The logic judgment unit is used for judging whether the optimal particle satisfies a preset selection rule or not. If so, optimal solution of the optimal particle is obtained. If not, the particle update unit is retriggered to update the inertia weight, the speed value and the location value of each particle of each layer of basic membrane according to the fitness value so as to obtain the optimal particle.