Provably good routing tree construction with multi-port terminals

Previous literature on VLSI routing and wiring estimation typically assumes a one-to-one correspondence between terminals and ports. In practice, however (say, in a gridded routing regime), each \terminal" consists of a large collection of electrically equivalent ports, a fact that is not accounted for in layout steps such as wiring estimation. The presence of multiple ports for a given terminal gives rise to the group Steiner minimal tree problem. In this paper, we address the general problem of minimum-cost routing tree construction in the presence of multi-port terminals. Our main result is the rst known heuristic with a sub-linear performance bound. In particular, for a net with k multi-port terminals, previous heuristics have a performance bound of (k 1) OPT , while our construction o ers an improved performance bound of (1 + ln k 2 ) pk OPT . Our Java implementation is available on the World Wide Web.