FPGA based echo delay control method for pulse radar testing

A compact and low-cost echo delay control method for pulse radar testing is proposed. Unlike the traditional delay technology based on surface acoustic wave (SAW) filter and fiber delay line, this paper provides a field programmable gate array (FPGA) based delay control method to fulfil the tasks of radar pulse acquisition, storage and delayed forwarding. Programmable resources of phase lock loops (PLL) and memories within the FPGA are used. Experiment results show that the proposed approach can be used for making a controllable pulse echo delay platform with the minimum delay step is less than 1ns, and the maximum delay time is greater than 200us.