Modeling multimedia workloads for embedded system design
暂无分享,去创建一个
[1] Thomas D. Burd,et al. The simulation and evaluation of dynamic voltage scaling algorithms , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).
[2] Soonhoi Ha,et al. Efficient Exploration of On-Chip Bus Architectures and Memory Allocation , 2004 .
[3] Seongsoo Lee,et al. Run-time voltage hopping for low-power real-time systems , 2000, DAC.
[4] Luca Benini,et al. Dynamic frequency scaling with buffer insertion for mixed workloads , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Wayne H. Wolf,et al. The future of multiprocessor systems-on-chips , 2004, Proceedings. 41st Design Automation Conference, 2004..
[6] Lothar Thiele,et al. A general framework for analysing system properties in platform-based embedded system designs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[7] Edward A. Lee,et al. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.
[8] Taewhan Kim,et al. Optimal voltage allocation techniques for dynamically variable voltage processors , 2003, DAC '03.
[9] Sang Ho Lee,et al. Dynamic buffer allocation in video-on-demand systems , 2001, SIGMOD '01.
[10] Taewhan Kim,et al. Optimal voltage allocation techniques for dynamically variable voltage processors , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[11] Karthik Dantu,et al. Frame-based dynamic voltage and frequency scaling for a MPEG decoder , 2002, ICCAD 2002.
[12] K.G. Shin,et al. On-line dynamic voltage scaling for hard real-time systems using the EDF algorithm , 2004, 25th IEEE International Real-Time Systems Symposium.
[13] Lothar Thiele,et al. Characterizing Variable Task Releases and Processor Capacities , 1999 .
[14] Lothar Thiele,et al. Quantitative Characterization of Event Streams in Analysis of Hard Real-Time Applications , 2004, Proceedings. RTAS 2004. 10th IEEE Real-Time and Embedded Technology and Applications Symposium, 2004..
[15] John P. Lehoczky,et al. Fixed priority scheduling of periodic task sets with arbitrary deadlines , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.
[16] Taewhan Kim,et al. Profile-based optimal intra-task voltage scheduling for hard real-time applications , 2004, Proceedings. 41st Design Automation Conference, 2004..
[17] Asawaree Kalavade,et al. A tool for performance estimation of networked embedded end-systems , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[18] Niraj K. Jha,et al. Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems , 2003, ICCAD 2003.
[19] Kaushik Roy,et al. Dynamic VTH Scaling Scheme for Active Leakage Power Reduction , 2002, DATE.
[20] Rolf Ernst,et al. Performance analysis for complex embedded applications , 2005, Int. J. Embed. Syst..
[21] Anantha Chandrakasan,et al. Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[22] Ken Nakamura,et al. Single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[23] Aloysius K. Mok,et al. A multiframe model for real-time tasks , 1996, 17th IEEE Real-Time Systems Symposium.
[24] André Seznec,et al. Choosing representative slices of program execution for microarchitecture simulations: a preliminary , 2000 .
[25] K. Kuchcinski,et al. A constructive algorithm for memory-aware task assignment and scheduling , 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).
[26] Kiyoung Choi,et al. Power conscious fixed priority scheduling for hard real-time systems , 1999, DAC '99.
[27] Lothar Thiele,et al. Performance evaluation of network processor architectures: combining simulation with analytical estimation , 2003, Comput. Networks.
[28] Edward A. Lee,et al. Dataflow process networks , 1995, Proc. IEEE.
[29] Santanu Dutta,et al. Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..
[30] Alan Jay Smith,et al. Design and characterization of the Berkeley multimedia workload , 2002, Multimedia Systems.
[31] Lothar Thiele,et al. Workload characterization model for tasks with variable execution demand , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[32] Niraj K. Jha,et al. COSYN: hardware-software co-synthesis of embedded systems , 1997, DAC.
[33] Jef L. van Meerbergen,et al. Memory arbitration and cache management in stream-based systems , 2000, DATE '00.
[34] Diana Marculescu,et al. Power and performance evaluation of globally asynchronous locally synchronous processors , 2002, ISCA.
[35] Wei Tsang Ooi,et al. Processor Frequency Selection in Energy-Aware SoC Platform Design for Multimedia Applications , 2004 .
[36] L. Thiele,et al. Representation of process mode correlation for scheduling , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[37] Evert-Jan D. Pol,et al. Robust media processing in a flexible and cost-effective network of multi-tasking coprocessors , 2002, Proceedings 14th Euromicro Conference on Real-Time Systems. Euromicro RTS 2002.
[38] Michael González Harbour,et al. Offset-based response time analysis of distributed systems scheduled under EDF , 2003, 15th Euromicro Conference on Real-Time Systems, 2003. Proceedings..
[39] F. Frances Yao,et al. A scheduling model for reduced CPU energy , 1995, Proceedings of IEEE 36th Annual Foundations of Computer Science.
[40] Niraj K. Jha,et al. CASPER: Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures , 1998, Proceedings Design, Automation and Test in Europe.
[41] Lui Sha,et al. Aperiodic task scheduling for Hard-Real-Time systems , 2006, Real-Time Systems.
[42] Steve Leibson,et al. Configurable processors: a new era in chip design , 2005, Computer.
[43] Alan Burns,et al. An extendible approach for analyzing fixed priority hard real-time tasks , 1994, Real-Time Systems.
[44] K. Keutzer,et al. System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[45] Joseph Y.-T. Leung,et al. On the complexity of fixed-priority scheduling of periodic, real-time tasks , 1982, Perform. Evaluation.
[46] H. Ali,et al. Task Scheduling in Multiprocessing Systems , 1995, Computer.
[47] Edward A. Lee,et al. Synthesis of Embedded Software from Synchronous Dataflow Specifications , 1999, J. VLSI Signal Process..
[48] Petru Eles,et al. Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[49] Aurel A. Lazar,et al. Modeling video sources for real-time scheduling , 2005, Multimedia Systems.
[50] Pradeep K. Dubey,et al. How Multimedia Workloads Will Change Processor Design , 1997, Computer.
[51] Kevin Skadron,et al. Control-theoretic dynamic frequency and voltage scaling for multimedia workloads , 2002, CASES '02.
[52] Petru Eles,et al. Schedulability analysis and optimization for the synthesis of multi-cluster distributed embedded systems , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[53] Jürgen Teich,et al. SPI - a system model for heterogeneously specified embedded systems , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[54] Petru Eles,et al. Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).
[55] Shekhar Y. Borkar,et al. Design challenges of technology scaling , 1999, IEEE Micro.
[56] Soonhoi Ha,et al. Dynamic voltage scheduling with buffers in low-power multimedia applications , 2004, TECS.
[57] Marco Spuri,et al. Implications of Classical Scheduling Results for Real-Time Systems , 1995, Computer.
[58] Lothar Thiele,et al. Rate analysis for streaming applications with on-chip buffer constraints , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
[59] Hiroto Yasuura,et al. Voltage scheduling problem for dynamically variable voltage processors , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).
[60] Om Prakash Gangwal,et al. A Heterogeneous Multiprocessor Architecture for Flexible Media Processing , 2002, IEEE Des. Test Comput..
[61] Lothar Thiele,et al. A Stream-Oriented Component Model for Performance Analysis of Multiprocessor DSPs , 2005 .
[62] Lothar Thiele,et al. Embedded Software in Network Processors - Models and Algorithms , 2001, EMSOFT.
[63] Luca Benini,et al. A survey of design techniques for system-level dynamic power management , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[64] Tei-Wei Kuo,et al. An approximation algorithm for energy-efficient scheduling on a chip multiprocessor , 2005, Design, Automation and Test in Europe.
[65] Michael L. Scott,et al. Dynamic frequency and voltage control for a multiple clock domain microarchitecture , 2002, MICRO.
[66] Soonhoi Ha,et al. Efficient exploration of on-chip bus architectures and memory allocation , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..
[67] Scott Shenker,et al. Scheduling for reduced CPU energy , 1994, OSDI '94.
[68] Dongkun Shin,et al. Low-energy intra-task voltage scheduling using static timing analysis , 2001, DAC '01.
[69] Axel Jantsch,et al. System design for DSP applications in transaction level modeling paradigm , 2004, Proceedings. 41st Design Automation Conference, 2004..
[70] Jürgen Teich,et al. Combining multiple models of computation for scheduling and allocation , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).
[71] Niraj K. Jha,et al. Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[72] Nobu Matsumoto,et al. A single-chip MPEG-2 codec based on customizable media embedded processor , 2003 .
[73] Miodrag Potkonjak,et al. Power optimization of variable voltage core-based systems , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[74] Niraj K. Jha,et al. Low power system scheduling and synthesis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[75] K. Sreenivasan,et al. On the construction of a representative synthetic workload , 1974, CACM.
[76] Fabian Wolf. Behavioral Intervals in Embedded Software: Timing and Power Analysis of Embedded Real-Time Software Processes , 2002 .
[77] Jun Sun,et al. Probabilistic performance guarantee for real-time tasks with varying computation times , 1995, Proceedings Real-Time Technology and Applications Symposium.
[78] Jean-Yves Le Boudec,et al. Network Calculus: A Theory of Deterministic Queuing Systems for the Internet , 2001 .
[79] Luca Benini,et al. Dynamic voltage scaling and power management for portable systems , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[80] Rudy Lauwereins,et al. Design, Automation, and Test in Europe , 2008 .
[81] Venkatesh Akella,et al. Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[82] Petru Eles,et al. System-Level Design Techniques for Energy-Efficient Embedded Systems , 2003, Springer US.
[83] Todd M. Austin,et al. SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.
[84] Steve Goddard,et al. A theory of rate-based execution , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).
[85] John A. Clark,et al. Holistic schedulability analysis for distributed hard real-time systems , 1994, Microprocess. Microprogramming.
[86] Andy D. Pimentel,et al. Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems , 2002, Embedded Processor Design Challenges.
[87] Rohit Jain,et al. Variability in the execution of multimedia applications and implications for architecture , 2001, ISCA 2001.
[88] Rami G. Melhem,et al. Scheduling with dynamic voltage/speed adjustment using slack reclamation in multi-processor real-time systems , 2001, Proceedings 22nd IEEE Real-Time Systems Symposium (RTSS 2001) (Cat. No.01PR1420).
[89] Larry L. Peterson,et al. Predicting MPEG execution times , 1998, SIGMETRICS '98/PERFORMANCE '98.
[90] Sujit Dey,et al. Dynamic Platform Management for Configurable Platform-Based System-on-Chips , 2003, ICCAD 2003.
[91] Kees G. W. Goossens,et al. Guaranteeing the Quality of Services in Networks on Chip , 2003, Networks on Chip.
[92] Wayne H. Wolf. Multimedia applications of multiprocessor systems-on-chips , 2005, Design, Automation and Test in Europe.
[93] Miodrag Potkonjak,et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[94] John P. Lehoczky,et al. Real-time queueing theory , 1996, 17th IEEE Real-Time Systems Symposium.
[95] Margaret Martonosi,et al. Formal online methods for voltage/frequency control in multiple clock domain microprocessors , 2004, ASPLOS XI.
[96] Hui Zhang,et al. Service disciplines for guaranteed performance service in packet-switching networks , 1995, Proc. IEEE.
[97] Edward A. Lee,et al. Compile-time scheduling of dynamic constructs in dataflow program graphs , 1997 .
[98] Lieven Eeckhout,et al. Workload design: selecting representative program-input pairs , 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.
[99] Ed F. Deprettere,et al. Fast and accurate multiprocessor architecture exploration with symbolic programs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[100] Krzysztof Kuchcinski,et al. LEneS: task scheduling for low-energy systems using variable supply voltage processors , 2001, ASP-DAC '01.
[101] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[102] Lothar Thiele,et al. Evaluating schedulers for multimedia processing on buffer-constrained SoC platforms , 2004, IEEE Design & Test of Computers.
[103] Wei Tsang Ooi,et al. Identifying "representative" workloads in designing MpSoC platforms for media processing , 2004, 2nd Workshop onEmbedded Systems for Real-Time Multimedia, 2004. ESTImedia 2004..
[104] Rolf Ernst,et al. A Formal Approach to MpSoC Performance Verification , 2003, Computer.
[105] Stephen P. Boyd,et al. Managing power consumption in networks on chips , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[106] Alberto L. Sangiovanni-Vincentelli,et al. A tool for describing and evaluating hierarchical real-time bus scheduling policies , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[107] Krithi Ramamritham,et al. Allocation and Scheduling of Precedence-Related Periodic Tasks , 1995, IEEE Trans. Parallel Distributed Syst..
[108] Ed F. Deprettere,et al. System level design with SPADE: an M-JPEG case study , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[109] Christoforos E. Kozyrakis,et al. A New Direction for Computer Architecture Research , 1998, Computer.
[110] Jan Madsen,et al. Embedded system synthesis under memory constraints , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).
[111] Soonhoi Ha,et al. Schedule-aware performance estimation of communication architecture for efficient design space exploration , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[112] Naresh K. Sinha,et al. Modern Control Systems , 1981, IEEE Transactions on Systems, Man, and Cybernetics.
[113] Gang Qu,et al. Energy reduction techniques for multimedia applications with tolerance to deadline misses , 2003, DAC.
[114] M. Potkonjak,et al. On-line scheduling of hard real-time tasks on variable voltage processor , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[115] J. Leung,et al. A Note on Preemptive Scheduling of Periodic, Real-Time Tasks , 1980, Inf. Process. Lett..
[116] Jay K. Strosnider,et al. The Deferrable Server Algorithm for Enhanced Aperiodic Responsiveness in Hard Real-Time Environments , 1987, IEEE Trans. Computers.
[117] Kevin Skadron,et al. Reducing multimedia decode power using feedback control , 2003, Proceedings 21st International Conference on Computer Design.
[118] Wei Tsang Ooi,et al. Processor frequency selection for SoC platforms for multimedia applications , 2004, 25th IEEE International Real-Time Systems Symposium.
[119] Thomas D. Burd,et al. Energy efficient CMOS microprocessor design , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.
[120] Colin J. Fidge,et al. Real-Time Schedulability Tests for Preemptive Multitasking , 2004, Real-Time Systems.
[121] Petru Eles,et al. Schedulability analysis of applications with stochastic task execution times , 2004, TECS.
[122] Luca Benini,et al. SystemC Cosimulation and Emulation of Multiprocessor SoC Designs , 2003, Computer.
[123] Trevor Mudge,et al. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.
[124] Miodrag Potkonjak,et al. On-line scheduling of hard real-time tasks on variable voltage processor , 1998, ICCAD.
[125] Alan Burns,et al. Real Time Scheduling Theory: A Historical Perspective , 2004, Real-Time Systems.
[126] Shashi Kumar,et al. On Packet Switched Networks for On-Chip Communication , 2003, Networks on Chip.
[127] M. F.,et al. Bibliography , 1985, Experimental Gerontology.
[128] Sanjoy K. Baruah,et al. A general model for recurring real-time tasks , 1998, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279).
[129] Raj Talluri,et al. Anatomy of a portable digital mediaprocessor , 2004, IEEE Micro.
[130] Niraj K. Jha,et al. Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems , 2003, ICCAD.
[131] Sujit Dey,et al. Dynamic Platform Management for Configurable Platform-Based System-on-Chips , 2003, ICCAD.
[132] Steve Goddard,et al. Managing Latency and Buffer Requirements in Processing Graph Chains , 2001, Comput. J..
[133] Massoud Pedram,et al. Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding , 2004, Proceedings. 41st Design Automation Conference, 2004..
[134] Y.-K. Kwok,et al. Static scheduling algorithms for allocating directed task graphs to multiprocessors , 1999, CSUR.
[135] Satish K. Tripathi,et al. On the characterization of VBR MPEG streams , 1997, SIGMETRICS '97.
[136] L. S. Nielsen,et al. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[137] Lothar Thiele,et al. Real-time calculus for scheduling hard real-time systems , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).
[138] James W. Layland,et al. Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.
[139] Wayne H. Wolf,et al. A task-level hierarchical memory model for system synthesis of multiprocessors , 1997, DAC.
[140] William J. Dally,et al. Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.
[141] Rajesh Gupta,et al. Profile-based dynamic voltage scheduling using program checkpoints , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[142] Ed F. Deprettere,et al. Exploring Embedded-Systems Architectures with Artemis , 2001, Computer.
[143] Lama H. Chandrasena,et al. An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).
[144] Lothar Thiele,et al. A new task model for streaming applications and its schedulability analysis , 2005, Design, Automation and Test in Europe.
[145] Giorgio C. Buttazzo,et al. Resource Reservation in Dynamic Real-Time Systems , 2004, Real-Time Systems.
[146] Niraj K. Jha,et al. MOCSYN: multiobjective core-based single-chip system synthesis , 1999, DATE '99.
[147] Petru Eles,et al. Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).
[148] Yongxin Zhu,et al. Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..
[149] Rolf Ernst,et al. TDMA time slot and turn optimization with evolutionary search techniques , 2005, Design, Automation and Test in Europe.
[150] Gilles Kahn,et al. The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.
[151] Klara Nahrstedt,et al. Integration of dynamic voltage scaling and soft real-time scheduling for open mobile systems , 2002, NOSSDAV '02.
[152] Sharad Malik,et al. Performance Analysis of Embedded Systems , 1996 .
[153] No Given. Open Multimedia Platform for Next-Generation Mobile Devices , 2003, PATMOS.
[154] Rajesh K. Gupta,et al. Leakage aware dynamic voltage scaling for real-time embedded systems , 2004, Proceedings. 41st Design Automation Conference, 2004..
[155] Anantha Chandrakasan,et al. Dynamic voltage scheduling using adaptive filtering of workload traces , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[156] Samarjit Chakraborty,et al. System-level timing analysis and scheduling for embedded packet processors , 2003 .
[157] Rolf Ernst,et al. Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[158] Lothar Thiele,et al. Characterizing workload correlations in multi processor hard real-time systems , 2005, 11th IEEE Real Time and Embedded Technology and Applications Symposium.
[159] L. Thiele,et al. Abstracting functionality for modular performance analysis of hard real-time systems , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[160] Hal Wasserman,et al. Comparing algorithm for dynamic speed-setting of a low-power CPU , 1995, MobiCom '95.
[161] Azer Bestavros,et al. Statistical rate monotonic scheduling , 1998, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279).
[162] Krisztián Flautner,et al. Automatic Performance Setting for Dynamic Voltage Scaling , 2001, MobiCom '01.
[163] Lothar Thiele,et al. A framework for evaluating design tradeoffs in packet processing architectures , 2002, DAC '02.
[164] J.L. van Meerbergen,et al. Heterogeneous multiprocessor for the management of real-time video and graphics streams , 2000, IEEE Journal of Solid-State Circuits.
[165] Hermann Kopetz,et al. Real-time systems , 2018, CSC '73.
[166] Alice C. Parker,et al. Synthesis of application-specific multiprocessor systems including memory components , 1994, J. VLSI Signal Process..
[167] Radu Marculescu,et al. On-chip traffic modeling and synthesis for MPEG-2 video applications , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[168] Petru Eles,et al. Performance estimation for embedded systems with data and control dependencies , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).
[169] Martin Naedele. On the modeling and evaluation of real time systems , 2000 .
[170] Petru Eles,et al. Quasi-static voltage scaling for energy minimization with time constraints , 2005, Design, Automation and Test in Europe.
[171] Jay K. Strosnider,et al. ENHANCED APERIODIC RESPONSIVENESS IN HARD REAL-TIME ENVIRONMENTS. , 1987, RTSS 1987.
[172] Shuvra S. Bhattacharyya,et al. Embedded Multiprocessors: Scheduling and Synchronization , 2000 .