High-level Synthesis based on Parallel Design Patterns using a Functional Language

Logic-circuit integration of a field-programmable gate array (FPGA) has grown considerably with improvements in semiconductor technology. High-level synthesis (HLS) is now widely used to implement complex FPGA applications to increase design efficiency, taking the place of typical register-transfer level (RTL) design. Most HLS tools support C-like languages such as C/C++, SystemC, OpenCL, and CUDA. However, coarse-grain parallelism from a C-like language cannot be extracted easily, hence some tools use explicitly parallel programming languages to design hardware. However, all such tools rely on the programmer to correctly parallelize and perform optimizations on the application, which often forces the programmer to acquire hardware-design knowledge. In this work, we propose an HLS environment for FPGAs using the embedded domain-specific language (DSL) of Haskell as the design language. Haskell is a pure functional language that has the features of referential transparency and no side effects. Hence, it is better for mapping to hardware. Higher-order functions such as map, zipWith, and reduce are useful for allowing a parallel design pattern to automatically extract parallelism in the design. In our environment, the embedded DSL program is compiled to the LLVM intermediate representation (LLVM IR), which is then integrated into the open-source HLS tool, LegUp. LegUp synthesizes the LLVM IR to Verilog HDL, which can be merged with the FPGA design tools of the FPGA vendor. The evaluation results show that our proposed implementation achieves 3.00 and 4.96 times speed-up in two benchmarks, array addition and summation of array, respectively, relative to a C-like language design.